A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence

A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence

This paper presents a DPA-resistant AES crypto engine. The DPA countermeasure circuit is combined with a self-generated random number generator to eliminate an extra circuit for generating random bits. The cell area for the DPA-resistant AES crypto engine is 0.104 mm 2 in UMC 90 nm CMOS technology,...

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Hauptverfasser: Po-Chun Liu, Ju-Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee
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Sprache:eng
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Correlation
Cryptography
Engines
Resistance
Ring oscillators
Throughput
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Ju-Hung Hsiao
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Chen-Yi Lee
description This paper presents a DPA-resistant AES crypto engine. The DPA countermeasure circuit is combined with a self-generated random number generator to eliminate an extra circuit for generating random bits. The cell area for the DPA-resistant AES crypto engine is 0.104 mm 2 in UMC 90 nm CMOS technology, which is only 6.2% larger than an unprotected AES engine. The maximum operating frequency of the AES engine is 255 MHz, resulting in 2.97 Gb/s throughput. Since the DPA countermeasure circuit works in parallel with the AES engine, no throughput degradation is incurred with the proposed architecture. The proposed DPA-resistant AES engine has significant improvements over previous state-of-the-art designs.
doi_str_mv 10.1109/ESSCIRC.2011.6044917
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subjects Correlation
Cryptography
Engines
Resistance
Ring oscillators
Throughput
title A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence
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