Variation tolerant digitally assisted high-speed IO PHY

Technology scaling leads to reduction of supply voltage and increase in random device variability and thus creates new challenges for analog design. A complete overhaul of the design approach at system architecture and circuit topology levels is necessary to keep the link robust and tolerant to low...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Roytman, E., Nagarajan, M., Shah, R., Xin Ma, Bedard, R., Munshi, K., Iknaian, R., Fengxiang Cai, Jian Xu, Devi, G. S., Vempada, P.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Clocks Feedback loop Jitter Microprocessors Receivers Resistors Transmitters
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