Latch-Based Performance Optimization for FPGAs

We explore using pulsed latches for timing optimization -- a first in the FPGA community. Pulsed latches are transparent latches driven by a clock with a non-standard (non-50%) duty cycle. We exploit existing functionality within commercial FPGA chips to implement latch-based optimizations that do n...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Bill Teng, Anderson, J. H.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	clock skew Clocks Delay Field programmable gate arrays Latches Optimization pulsed-latch Routing time borrowing timing optimization
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