Design Framework for Soft-Error-Resilient Sequential Cells

Design Framework for Soft-Error-Resilient Sequential Cells

This paper presents a design framework for soft-error-resilient sequential cells, by introducing a new sequential cell called LEAP-DICE and evaluating it against existing circuit techniques in the "soft error resilience-power-delay-area" design space in an 180 nm CMOS test chip. LEAP-DICE,...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on nuclear science 2011-12, Vol.58 (6), p.3026-3032
Hauptverfasser: Lee, H.-H K., Lilja, K., Bounasser, M., Linscott, I., Inan, U.
Format: Artikel
Sprache:eng
Schlagworte:
Chips (electronics)
Circuit design
CMOS
CMOS integrated circuits
Costs
DICE
Flip-flops
Latches
Layout
LEAP
Radiation hardening
Resilience
Sequential circuits
soft error
Soft errors
Transistors
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:This paper presents a design framework for soft-error-resilient sequential cells, by introducing a new sequential cell called LEAP-DICE and evaluating it against existing circuit techniques in the "soft error resilience-power-delay-area" design space in an 180 nm CMOS test chip. LEAP-DICE, which employs both circuit and layout techniques, achieved the best soft error performance with a 2,000X improvement over the reference D flip-flop with moderate design costs. This study also discovered new soft error effects related to operating conditions.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2011.2168611