On fault probabilities and yield models for VLSI neural networks

We investigate the estimation of fault probabilities and yield for very large scale integration (VLSI) implementations of neural computational models. Our analysis is limited to structures that can be mapped directly onto silicon as truly distributed parallel processing systems. Our work improves on...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1997-08, Vol.32 (8), p.1284-1287
Hauptverfasser:	Furth, P.M., Andreou, A.G.
Format:	Artikel
Sprache:	eng
Schlagworte:	Circuit faults Computational modeling Distributed processing Fault tolerant systems Neural network hardware Neural networks Parallel processing Silicon Very large scale integration Yield estimation
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