On fault probabilities and yield models for VLSI neural networks
We investigate the estimation of fault probabilities and yield for very large scale integration (VLSI) implementations of neural computational models. Our analysis is limited to structures that can be mapped directly onto silicon as truly distributed parallel processing systems. Our work improves on...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1997-08, Vol.32 (8), p.1284-1287 |
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| container_end_page | 1287 |
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| container_issue | 8 |
| container_start_page | 1284 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 32 |
| creator | Furth, P.M. Andreou, A.G. |
| description | We investigate the estimation of fault probabilities and yield for very large scale integration (VLSI) implementations of neural computational models. Our analysis is limited to structures that can be mapped directly onto silicon as truly distributed parallel processing systems. Our work improves on the framework suggested by Feltham and Maly and is also applicable to analog or mixed analog/digital VLSI systems. |
| doi_str_mv | 10.1109/4.604090 |
| format | Article |
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| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 1997-08, Vol.32 (8), p.1284-1287 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_ieee_primary_604090 |
| source | IEEE Electronic Library (IEL) |
| subjects | Circuit faults Computational modeling Distributed processing Fault tolerant systems Neural network hardware Neural networks Parallel processing Silicon Very large scale integration Yield estimation |
| title | On fault probabilities and yield models for VLSI neural networks |
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