Analog circuits sizing using bipartite graphs

This paper presents a new formalization of a hierarchical methodology for the sizing and biasing of analog IPs using bipartite directed acyclic graphs. This methodology allows to generate suitable sizing procedures that respect designer hypothesis and circuit topology. A library of simulator-based s...

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Bibliographische Detailangaben

Hauptverfasser:	Javid, F., Iskander, R., Louerat, Marie-Minerve, Dupuis, D.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Computer Science
Online-Zugang:	Volltext bestellen
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