High-speed architecture for k-dimensional LFSR in H/W implementation

Proposal for a high-speed architecture of Linear Feedback Shift Registers (LFSR), related to the hardware implementation of pseudo-random Gold-sequence, is presented here. In high-speed communication systems, a scrambling of large coded bits is difficult to compute using a conventional LFSR architec...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Chan-Bok Jeong, Dae-Ho Kim, Hyeon-Deok Bae
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Binary phase shift keying Clocks Timing Very large scale integration
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!