A modified background calibration technique for multi-bit delta-sigma modulators
A digital background calibration technique for capacitors mismatch in multi-bit delta-sigma modulator is proposed in this paper. The approach is correlation-based, in which a single-bit pseudo-random noise (PN) is used to identify the error module, minimizing the analog circuit overhead. This algori...
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| creator | Bei Peng Hao Li Pingfen Lin |
| description | A digital background calibration technique for capacitors mismatch in multi-bit delta-sigma modulator is proposed in this paper. The approach is correlation-based, in which a single-bit pseudo-random noise (PN) is used to identify the error module, minimizing the analog circuit overhead. This algorithm works by estimating every DAC capacitor in turn with the PN signal injection and compensates for capacitor mismatch in digital domain. It is simple and requires minor circuit modification in analog domain. The tradeoff involved is the dynamic range degradation due to PN injection. Behavior level simulations demonstrate effective compensation for capacitors mismatch in a second-order modulator. |
| doi_str_mv | 10.1109/ICACC.2011.6016398 |
| format | Conference Proceeding |
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The approach is correlation-based, in which a single-bit pseudo-random noise (PN) is used to identify the error module, minimizing the analog circuit overhead. This algorithm works by estimating every DAC capacitor in turn with the PN signal injection and compensates for capacitor mismatch in digital domain. It is simple and requires minor circuit modification in analog domain. The tradeoff involved is the dynamic range degradation due to PN injection. Behavior level simulations demonstrate effective compensation for capacitors mismatch in a second-order modulator.</description><identifier>ISBN: 1424488095</identifier><identifier>ISBN: 9781424488094</identifier><identifier>EISBN: 1424488109</identifier><identifier>EISBN: 9781424488100</identifier><identifier>DOI: 10.1109/ICACC.2011.6016398</identifier><language>eng</language><publisher>IEEE</publisher><subject>Calibration ; Capacitor mismatch ; Delta-Sigma modulator ; digital calibration ; Modulation ; PN sequence ; SNDR</subject><ispartof>2011 3rd International Conference on Advanced Computer Control, 2011, p.206-208</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6016398$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6016398$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Bei Peng</creatorcontrib><creatorcontrib>Hao Li</creatorcontrib><creatorcontrib>Pingfen Lin</creatorcontrib><title>A modified background calibration technique for multi-bit delta-sigma modulators</title><title>2011 3rd International Conference on Advanced Computer Control</title><addtitle>ICACC</addtitle><description>A digital background calibration technique for capacitors mismatch in multi-bit delta-sigma modulator is proposed in this paper. The approach is correlation-based, in which a single-bit pseudo-random noise (PN) is used to identify the error module, minimizing the analog circuit overhead. This algorithm works by estimating every DAC capacitor in turn with the PN signal injection and compensates for capacitor mismatch in digital domain. It is simple and requires minor circuit modification in analog domain. The tradeoff involved is the dynamic range degradation due to PN injection. Behavior level simulations demonstrate effective compensation for capacitors mismatch in a second-order modulator.</description><subject>Calibration</subject><subject>Capacitor mismatch</subject><subject>Delta-Sigma modulator</subject><subject>digital calibration</subject><subject>Modulation</subject><subject>PN sequence</subject><subject>SNDR</subject><isbn>1424488095</isbn><isbn>9781424488094</isbn><isbn>1424488109</isbn><isbn>9781424488100</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo9kMtKxDAYhSMiqOO8gG7yAq25_M1lORR1hAFdzH5Imz9jtBdN04Vvb8XBszkcDnwcDiG3nJWcM3v_XG_quhSM81IxrqQ1Z-SagwAwZunP_wOz1SVZT9M7W6SE1ppfkdcN7UcfQ0RPG9d-HNM4D562rotNcjmOA83Yvg3xa0YaxkT7ucuxaGKmHrvsiikee_fLmDuXxzTdkIvgugnXJ1-R_ePDvt4Wu5enZequiJblAgRHHpiQzBqlGg3GC28CZ2DBeQPcGeNdhVJX0DCJy2AVjIbWWkAGXq7I3R82IuLhM8Xepe_D6QD5A5BgTvg</recordid><startdate>201101</startdate><enddate>201101</enddate><creator>Bei Peng</creator><creator>Hao Li</creator><creator>Pingfen Lin</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201101</creationdate><title>A modified background calibration technique for multi-bit delta-sigma modulators</title><author>Bei Peng ; Hao Li ; Pingfen Lin</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-421e1f02309866b748d2d8f10494ad841a88da5e3754b03e0066f874c994e04d3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Calibration</topic><topic>Capacitor mismatch</topic><topic>Delta-Sigma modulator</topic><topic>digital calibration</topic><topic>Modulation</topic><topic>PN sequence</topic><topic>SNDR</topic><toplevel>online_resources</toplevel><creatorcontrib>Bei Peng</creatorcontrib><creatorcontrib>Hao Li</creatorcontrib><creatorcontrib>Pingfen Lin</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Bei Peng</au><au>Hao Li</au><au>Pingfen Lin</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A modified background calibration technique for multi-bit delta-sigma modulators</atitle><btitle>2011 3rd International Conference on Advanced Computer Control</btitle><stitle>ICACC</stitle><date>2011-01</date><risdate>2011</risdate><spage>206</spage><epage>208</epage><pages>206-208</pages><isbn>1424488095</isbn><isbn>9781424488094</isbn><eisbn>1424488109</eisbn><eisbn>9781424488100</eisbn><abstract>A digital background calibration technique for capacitors mismatch in multi-bit delta-sigma modulator is proposed in this paper. The approach is correlation-based, in which a single-bit pseudo-random noise (PN) is used to identify the error module, minimizing the analog circuit overhead. This algorithm works by estimating every DAC capacitor in turn with the PN signal injection and compensates for capacitor mismatch in digital domain. It is simple and requires minor circuit modification in analog domain. The tradeoff involved is the dynamic range degradation due to PN injection. Behavior level simulations demonstrate effective compensation for capacitors mismatch in a second-order modulator.</abstract><pub>IEEE</pub><doi>10.1109/ICACC.2011.6016398</doi><tpages>3</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Calibration Capacitor mismatch Delta-Sigma modulator digital calibration Modulation PN sequence SNDR |
| title | A modified background calibration technique for multi-bit delta-sigma modulators |
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