MTASC: A Multithreaded Associative SIMD Processor

In this paper we describe the architecture of MTASC, a multithreaded associative SIMD processor, and a cycle-accurate instruction set simulator for that architecture. We show, through simulations of a set of five associative benchmarks, that this architecture is capable of significantly improving th...

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Bibliographische Detailangaben

Hauptverfasser:	Schaffer, K., Walker, R. A.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Arrays Benchmark testing Hardware Instruction sets Multithreading Registers
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