Variability-aware task mapping strategies for many-cores processor chips

The advent of the Deep Submicron technology opens the way to many-cores processor chips. However, the variability and reliability of these processes poses new challenges. In particular, the mapping of applications will require specific strategies to leverage the plenty and diversity of the computation cores. In this work, a high-level study of the variability impact on Thousands-core processors is proposed for future technologies, based on the state-of-art VARIUS model. While many crucial details are yet unknown for these technologies, we suggest several scenarios, based on the existing literature. The obtained results are particularily suitable for Embedded Streaming applications, which both require high performance and low energy consumption. In this regard, generic task mapping strategies are proposed to improve the energy efficiency of the applications, and compared for a synthetic application. The Nearest node strategy is used as a baseline, and minimizes the communication overhead. Then, a novel energy criterion is introduced to balance the computation and communication energy consumption. While increasing the communication energy, this strategy reduces the overall consumption by up to 20%. Finally, a mapping strategy based on variability regions improves slightly the energy efficiency of the application in the presence of systematic variations.