A dynamic body-biased SRAM with asymmetric halo implant MOSFETs
In this paper, we propose an SRAM macro that realizes 0.5V operation by combining a device technique with simple design architecture. Regarding the device technique, we utilize asymmetric halo implant MOSFETs, which enables to enhance both the static noise margin and write margin of SRAM, simultaneo...
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| creator | Yabuuchi, M. Tsukamoto, Y. Fujiwara, H. Tawa, S. Maekawa, K. Igarashi, M. Nii, K. |
| description | In this paper, we propose an SRAM macro that realizes 0.5V operation by combining a device technique with simple design architecture. Regarding the device technique, we utilize asymmetric halo implant MOSFETs, which enables to enhance both the static noise margin and write margin of SRAM, simultaneously. As for the design technique, dynamic body-bias scheme which operates body bias dynamically is introduced to overcome the speed degradation due to lower supply voltage. Showing measured data fabricated on 45nm CMOS technology, we demonstrate a plausible scenario for achieving 0.5V operating SoC products. |
| doi_str_mv | 10.1109/ISLPED.2011.5993651 |
| format | Conference Proceeding |
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Showing measured data fabricated on 45nm CMOS technology, we demonstrate a plausible scenario for achieving 0.5V operating SoC products.</description><subject>asymmetric MOSFET</subject><subject>Bit rate</subject><subject>dynamic body-bias</subject><subject>Layout</subject><subject>Logic gates</subject><subject>MOSFETs</subject><subject>Random access memory</subject><subject>SRAM</subject><subject>Substrates</subject><subject>variation</subject><isbn>9781612846583</isbn><isbn>1612846580</isbn><isbn>9781612846590</isbn><isbn>9781612846606</isbn><isbn>1612846602</isbn><isbn>1612846599</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVj89Kw0AYxFdEUGqeoJd9gcTvyyab7ElCrVpIqZjey_6lK9m2ZAOStzdgL53LMD-GgSFkiZAhgnjZdO3X-i3LATErhWC8xDuSiKpGjnld8FLA_U2u2SNJYvyBWZwLAfhEXhtqppMMXlN1NlOqvIzW0O672dJfPx6pjFMIdhzmwlH2Z-rDpZenkW533ft6H5_Jg5N9tMnVF2Q_49Vn2u4-NqumTb2AMbVMK4EgtTFQgna5Uo4bo6wzjlVoCldYZAocx6qAOteyVBWvDRimgaNiC7L8n_XW2sNl8EEO0-H6mv0BG0RLDA</recordid><startdate>201108</startdate><enddate>201108</enddate><creator>Yabuuchi, M.</creator><creator>Tsukamoto, Y.</creator><creator>Fujiwara, H.</creator><creator>Tawa, S.</creator><creator>Maekawa, K.</creator><creator>Igarashi, M.</creator><creator>Nii, K.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201108</creationdate><title>A dynamic body-biased SRAM with asymmetric halo implant MOSFETs</title><author>Yabuuchi, M. ; Tsukamoto, Y. ; Fujiwara, H. ; Tawa, S. ; Maekawa, K. ; Igarashi, M. ; Nii, K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-e3cb910acdd050cf2bbf6ddbefdf371d4f4e13b0f6174082ca5b768d0d3c061b3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>asymmetric MOSFET</topic><topic>Bit rate</topic><topic>dynamic body-bias</topic><topic>Layout</topic><topic>Logic gates</topic><topic>MOSFETs</topic><topic>Random access memory</topic><topic>SRAM</topic><topic>Substrates</topic><topic>variation</topic><toplevel>online_resources</toplevel><creatorcontrib>Yabuuchi, M.</creatorcontrib><creatorcontrib>Tsukamoto, Y.</creatorcontrib><creatorcontrib>Fujiwara, H.</creatorcontrib><creatorcontrib>Tawa, S.</creatorcontrib><creatorcontrib>Maekawa, K.</creatorcontrib><creatorcontrib>Igarashi, M.</creatorcontrib><creatorcontrib>Nii, K.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yabuuchi, M.</au><au>Tsukamoto, Y.</au><au>Fujiwara, H.</au><au>Tawa, S.</au><au>Maekawa, K.</au><au>Igarashi, M.</au><au>Nii, K.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A dynamic body-biased SRAM with asymmetric halo implant MOSFETs</atitle><btitle>IEEE/ACM International Symposium on Low Power Electronics and Design</btitle><stitle>ISLPED</stitle><date>2011-08</date><risdate>2011</risdate><spage>285</spage><epage>290</epage><pages>285-290</pages><isbn>9781612846583</isbn><isbn>1612846580</isbn><eisbn>9781612846590</eisbn><eisbn>9781612846606</eisbn><eisbn>1612846602</eisbn><eisbn>1612846599</eisbn><abstract>In this paper, we propose an SRAM macro that realizes 0.5V operation by combining a device technique with simple design architecture. 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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | asymmetric MOSFET Bit rate dynamic body-bias Layout Logic gates MOSFETs Random access memory SRAM Substrates variation |
| title | A dynamic body-biased SRAM with asymmetric halo implant MOSFETs |
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