High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement

In this paper, we propose a run-time strategy for managing writes onto last level cache in chip multiprocessors where STT-RAM memory is used as baseline technology. To this end, we assume that each cache set is decomposed into limited SRAM lines and large number of STT-RAM lines. SRAM lines are targ...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Jadidi, A., Arjomand, M., Sarbazi-Azad, H.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	cache line displacement chip multiprocessors Computer architecture hybrid cache architecture Indexes Integrated circuit modeling Magnetic tunneling Microprocessors Radiation detectors Random access memory spin torque transfer RAM wear leveling
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