PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs

In this paper, we introduce an integrated power methodology for multi-core SoC designs. It features not only a bottom-up IP-based power modeling for all kinds of IP components ranging from hardware accelerators, processors, and memory blocks, but also a top-down system-wide ESL power estimation form...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Hsu, Chen-Wei, Liao, Jia-Lu, Fang, Shan-Chien, Weng, Chia-Chien, Huang, Shi-Yu, Hsieh, Wen-Tsan, Yeh, Jen-Chieh
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Estimation Hardware > Hardware validation IP networks IP-based power modeling Load modeling Logic gates Monitoring Program processors System-level power analysis System-on-a-chip
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