Quadrant-based XYZ dimension order routing algorithm for 3-D Asymmetric Torus Routing Chip (ATRC)

The conventional two-dimensional (2-D) integrated circuit (IC) has limited scope for floor planning and therefore limits the performance improvements resulting from the Network-on-Chip (NoC) paradigm. Three Dimensional (3-D) ICs are able to obtain significant performance benefits over 2-D ICs based...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Khan, M. A., Ansari, A. Q.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	3-D Algorithm design and analysis Asmmetric torus Computational modeling Computer architecture Integrated circuit interconnections Mesh networks NoC Partitioning algorithms Routing RTL XYZ
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