A duty cycle corrector based frequency multiplier

A duty cycle corrector based frequency multiplier

In this paper a modified frequency multiplier based on a low power duty cycle corrector is presented. The proposed circuit multiplies the output frequency of a PLL, by 3. Also, the output duty cycle of the multiplier could be controlled by changing the ratio of charging/discharging current of the ch...

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Hauptverfasser: Navidi, M. M., Abrishamifar, A.
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Sprache:eng
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Duty Cycle Correction
Frequency multiplier
Voltage Controlled Oscillator
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Abrishamifar, A.
description In this paper a modified frequency multiplier based on a low power duty cycle corrector is presented. The proposed circuit multiplies the output frequency of a PLL, by 3. Also, the output duty cycle of the multiplier could be controlled by changing the ratio of charging/discharging current of the charge pump. This circuit is simulated by using 0.18 um CMOS process. When the VCO operates at 846MHz the power dissipation of the circuit is 1.16mW at 1.8V supply voltage.
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M. ; Abrishamifar, A.</creatorcontrib><description>In this paper a modified frequency multiplier based on a low power duty cycle corrector is presented. The proposed circuit multiplies the output frequency of a PLL, by 3. Also, the output duty cycle of the multiplier could be controlled by changing the ratio of charging/discharging current of the charge pump. This circuit is simulated by using 0.18 um CMOS process. When the VCO operates at 846MHz the power dissipation of the circuit is 1.16mW at 1.8V supply voltage.</description><identifier>ISSN: 2164-7054</identifier><identifier>ISBN: 1457707306</identifier><identifier>ISBN: 9781457707308</identifier><identifier>EISBN: 9644634284</identifier><identifier>EISBN: 9789644634284</identifier><language>eng</language><publisher>IEEE</publisher><subject>Duty Cycle Correction ; Frequency multiplier ; Voltage Controlled Oscillator</subject><ispartof>2011 19th Iranian Conference on Electrical Engineering, 2011, p.1-1</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5955838$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5955838$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Navidi, M. M.</creatorcontrib><creatorcontrib>Abrishamifar, A.</creatorcontrib><title>A duty cycle corrector based frequency multiplier</title><title>2011 19th Iranian Conference on Electrical Engineering</title><addtitle>IranianCEE</addtitle><description>In this paper a modified frequency multiplier based on a low power duty cycle corrector is presented. The proposed circuit multiplies the output frequency of a PLL, by 3. Also, the output duty cycle of the multiplier could be controlled by changing the ratio of charging/discharging current of the charge pump. This circuit is simulated by using 0.18 um CMOS process. When the VCO operates at 846MHz the power dissipation of the circuit is 1.16mW at 1.8V supply voltage.</description><subject>Duty Cycle Correction</subject><subject>Frequency multiplier</subject><subject>Voltage Controlled Oscillator</subject><issn>2164-7054</issn><isbn>1457707306</isbn><isbn>9781457707308</isbn><isbn>9644634284</isbn><isbn>9789644634284</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9yb0OgjAUQOFr1ERQnsClL0DS0l9GYzQ-gDvBcklqimALQ99eB2fP8g1nBXmthFBcVEasIWdCak01p2oDWcWUKDWVYgdFjE_6TamaGZ0BO5FumROxyXokdgwB7TwG8mgjdqQP-F7wZRMZFj-7yTsMB9j2rY9Y_NzD8Xq5n2-lQ8RmCm5oQ2pkLaXhhv-_H0K2MjM</recordid><startdate>201105</startdate><enddate>201105</enddate><creator>Navidi, M. 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M.</creatorcontrib><creatorcontrib>Abrishamifar, A.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Navidi, M. M.</au><au>Abrishamifar, A.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A duty cycle corrector based frequency multiplier</atitle><btitle>2011 19th Iranian Conference on Electrical Engineering</btitle><stitle>IranianCEE</stitle><date>2011-05</date><risdate>2011</risdate><spage>1</spage><epage>1</epage><pages>1-1</pages><issn>2164-7054</issn><isbn>1457707306</isbn><isbn>9781457707308</isbn><eisbn>9644634284</eisbn><eisbn>9789644634284</eisbn><abstract>In this paper a modified frequency multiplier based on a low power duty cycle corrector is presented. The proposed circuit multiplies the output frequency of a PLL, by 3. Also, the output duty cycle of the multiplier could be controlled by changing the ratio of charging/discharging current of the charge pump. This circuit is simulated by using 0.18 um CMOS process. When the VCO operates at 846MHz the power dissipation of the circuit is 1.16mW at 1.8V supply voltage.</abstract><pub>IEEE</pub></addata></record>
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subjects Duty Cycle Correction
Frequency multiplier
Voltage Controlled Oscillator
title A duty cycle corrector based frequency multiplier
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