Tool Chain Support with Dynamic Profiling for RISP
This article proposes a concept of dynamic profiling reconfigurable instruction set processor (RISP) and related retargetable tool chain support. The tool chain consists of a profiler, a code mapper, and a retargetable compiler. Firstly dynamic profiler is employed to obtain hot path for application...
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| creator | Chao Wang Huizhen Zhang Xuehai Zhou Jinsong Ji Aili Wang |
| description | This article proposes a concept of dynamic profiling reconfigurable instruction set processor (RISP) and related retargetable tool chain support. The tool chain consists of a profiler, a code mapper, and a retargetable compiler. Firstly dynamic profiler is employed to obtain hot path for applications. Then hot block is implemented in reconfiguration logic units. After newly designed hardware block is integrated into system, mapper supplies a mechanism to map hot blocks to hardware implementations. Retargetable compiler is used for recompilation and regenerating executable binary code. The three modules have been demonstrated on simulation platform separately. Experimental result in previous work has already demonstrated the profiler can reach 97% of accuracy. A prototype code map per shows the feasibility of the mapping mechanism. The simulation results of retargetable compiler shows with the decrease of code size and reconfiguration time, application can still be largely accelerated by RISP processor. |
| doi_str_mv | 10.1109/ISPA.2011.39 |
| format | Conference Proceeding |
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The tool chain consists of a profiler, a code mapper, and a retargetable compiler. Firstly dynamic profiler is employed to obtain hot path for applications. Then hot block is implemented in reconfiguration logic units. After newly designed hardware block is integrated into system, mapper supplies a mechanism to map hot blocks to hardware implementations. Retargetable compiler is used for recompilation and regenerating executable binary code. The three modules have been demonstrated on simulation platform separately. Experimental result in previous work has already demonstrated the profiler can reach 97% of accuracy. A prototype code map per shows the feasibility of the mapping mechanism. The simulation results of retargetable compiler shows with the decrease of code size and reconfiguration time, application can still be largely accelerated by RISP processor.</description><identifier>ISSN: 2158-9178</identifier><identifier>ISBN: 1457703912</identifier><identifier>ISBN: 9781457703911</identifier><identifier>EISBN: 0769544282</identifier><identifier>EISBN: 9780769544281</identifier><identifier>DOI: 10.1109/ISPA.2011.39</identifier><language>eng</language><publisher>IEEE</publisher><subject>Accuracy ; Arrays ; code mapping ; dynamic profiling ; Field programmable gate arrays ; Hardware ; reconfigurable instruction set processor ; retargetable compilation ; Software tools</subject><ispartof>2011 IEEE Ninth International Symposium on Parallel and Distributed Processing with Applications, 2011, p.155-160</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5951898$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,778,782,787,788,2054,27908,54903</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5951898$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Chao Wang</creatorcontrib><creatorcontrib>Huizhen Zhang</creatorcontrib><creatorcontrib>Xuehai Zhou</creatorcontrib><creatorcontrib>Jinsong Ji</creatorcontrib><creatorcontrib>Aili Wang</creatorcontrib><title>Tool Chain Support with Dynamic Profiling for RISP</title><title>2011 IEEE Ninth International Symposium on Parallel and Distributed Processing with Applications</title><addtitle>ispa</addtitle><description>This article proposes a concept of dynamic profiling reconfigurable instruction set processor (RISP) and related retargetable tool chain support. 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The simulation results of retargetable compiler shows with the decrease of code size and reconfiguration time, application can still be largely accelerated by RISP processor.</description><subject>Accuracy</subject><subject>Arrays</subject><subject>code mapping</subject><subject>dynamic profiling</subject><subject>Field programmable gate arrays</subject><subject>Hardware</subject><subject>reconfigurable instruction set processor</subject><subject>retargetable compilation</subject><subject>Software tools</subject><issn>2158-9178</issn><isbn>1457703912</isbn><isbn>9781457703911</isbn><isbn>0769544282</isbn><isbn>9780769544281</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjb1OwzAYAI0AibZ0Y2PxCyR8n_89VoFCpUpUNHvlxA41SpPICUJ9eyrBLbfdEfKAkCOCfdrsd6ucAWLO7RWZg1ZWCsEMuyZzFFJr4BbZDZkxlCazqM0dWY7jF1xQygrFZ4SVfd_S4uhiR_ffw9Cnif7E6Uifz507xZruUt_ENnaftOkT_bg878lt49oxLP-9IOX6pSzesu3766ZYbbNoYcqEqRuPwDV4VwWHHJQJulZgHQOnfe2Vx0YGZ7QKngldMR8kB2lCrStgfEEe_7IxhHAYUjy5dD5IK9FYw38ByGNE3w</recordid><startdate>201105</startdate><enddate>201105</enddate><creator>Chao Wang</creator><creator>Huizhen Zhang</creator><creator>Xuehai Zhou</creator><creator>Jinsong Ji</creator><creator>Aili Wang</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201105</creationdate><title>Tool Chain Support with Dynamic Profiling for RISP</title><author>Chao Wang ; Huizhen Zhang ; Xuehai Zhou ; Jinsong Ji ; Aili Wang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-48cfd10370dabea13068e7c609a20a7dcd6d1f5ea876ed247b2de53058ec7b023</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Accuracy</topic><topic>Arrays</topic><topic>code mapping</topic><topic>dynamic profiling</topic><topic>Field programmable gate arrays</topic><topic>Hardware</topic><topic>reconfigurable instruction set processor</topic><topic>retargetable compilation</topic><topic>Software tools</topic><toplevel>online_resources</toplevel><creatorcontrib>Chao Wang</creatorcontrib><creatorcontrib>Huizhen Zhang</creatorcontrib><creatorcontrib>Xuehai Zhou</creatorcontrib><creatorcontrib>Jinsong Ji</creatorcontrib><creatorcontrib>Aili Wang</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chao Wang</au><au>Huizhen Zhang</au><au>Xuehai Zhou</au><au>Jinsong Ji</au><au>Aili Wang</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Tool Chain Support with Dynamic Profiling for RISP</atitle><btitle>2011 IEEE Ninth International Symposium on Parallel and Distributed Processing with Applications</btitle><stitle>ispa</stitle><date>2011-05</date><risdate>2011</risdate><spage>155</spage><epage>160</epage><pages>155-160</pages><issn>2158-9178</issn><isbn>1457703912</isbn><isbn>9781457703911</isbn><eisbn>0769544282</eisbn><eisbn>9780769544281</eisbn><abstract>This article proposes a concept of dynamic profiling reconfigurable instruction set processor (RISP) and related retargetable tool chain support. The tool chain consists of a profiler, a code mapper, and a retargetable compiler. Firstly dynamic profiler is employed to obtain hot path for applications. Then hot block is implemented in reconfiguration logic units. After newly designed hardware block is integrated into system, mapper supplies a mechanism to map hot blocks to hardware implementations. Retargetable compiler is used for recompilation and regenerating executable binary code. The three modules have been demonstrated on simulation platform separately. Experimental result in previous work has already demonstrated the profiler can reach 97% of accuracy. A prototype code map per shows the feasibility of the mapping mechanism. The simulation results of retargetable compiler shows with the decrease of code size and reconfiguration time, application can still be largely accelerated by RISP processor.</abstract><pub>IEEE</pub><doi>10.1109/ISPA.2011.39</doi><tpages>6</tpages></addata></record> |
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| identifier | ISSN: 2158-9178 |
| ispartof | 2011 IEEE Ninth International Symposium on Parallel and Distributed Processing with Applications, 2011, p.155-160 |
| issn | 2158-9178 |
| language | eng |
| recordid | cdi_ieee_primary_5951898 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Accuracy Arrays code mapping dynamic profiling Field programmable gate arrays Hardware reconfigurable instruction set processor retargetable compilation Software tools |
| title | Tool Chain Support with Dynamic Profiling for RISP |
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