Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics
Reliable and scalable manufacturing of nanofabrics entails significant challenges. Scalable nanomanufacturing approaches that employ the use of lithographic masks in conjunction with nanofabrication based on self-assembly have been proposed. A bottom-up fabrication of nanoelectronic circuits is expe...
Gespeichert in:
Hauptverfasser: | , , , , |
---|---|
Format: | Tagungsbericht |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 188 |
---|---|
container_issue | |
container_start_page | 181 |
container_title | |
container_volume | |
creator | Vijayakumar, Priyamvada Narayanan, Pritish Koren, Israel Mani Krishna, C. Moritz, Csaba Andras |
description | Reliable and scalable manufacturing of nanofabrics entails significant challenges. Scalable nanomanufacturing approaches that employ the use of lithographic masks in conjunction with nanofabrication based on self-assembly have been proposed. A bottom-up fabrication of nanoelectronic circuits is expected to be subject to various defects and identifying the types of defects that may occur during each step of a manufacturing pathway is essential in any attempt to achieve reliable manufacturing. The paper proposes a methodology for analyzing the sources of defects in a nano-manufacturing flow and estimating the resulting systematic yield loss. This methodology allows analyzing the impact of the fabrication process on the systematic yield. It integrates physical fabric considerations, manufacturing sequences and the resulting defect scenarios. This is in contrast to most current approaches that use conventional defect models and assume constant defect rates without analyzing the manufacturing pathway to determine the sources of defects and their probabilities (or rates). While the focus of the paper is on estimating the mask overlay-limited yield for the NASIC nano-fabric, the proposed approach can be easily adapted to suit other structured nano-fabrics. |
doi_str_mv | 10.1109/NANOARCH.2011.5941502 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>acm_6IE</sourceid><recordid>TN_cdi_ieee_primary_5941502</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5941502</ieee_id><sourcerecordid>acm_books_10_1109_NANOARCH_2011_5941502</sourcerecordid><originalsourceid>FETCH-LOGICAL-a229t-f36eb41c14a992c412d03b1bb8322c68175fc1e175c699c16bb83f2d068b1daa3</originalsourceid><addsrcrecordid>eNqVkNtKAzEQhuMJrLVPIEJeYNdMks0ml6VYWyitiF6HJE1kdQ9ls0X69m5tK946N8PwzT8wH0L3QFIAoh6W4-Vq_DKZpZQApJnikBF6hkYql8CzPCdKcX6OBpTRPJGUigt0cwIsv_wFIK_RKMYP0pcQiik5QM_zamNch5uAa1M3lam3oZ-3bVG_41A2X7ipcdzFzlemKxzeFb5c47KJ0Udc1D-h6EzpcTC2LVy8RVfBlNGPjn2I3qaPr5NZslg9zSfjRWIoVV0SmPCWgwNulKKOA10TZsFaySh1QkKeBQe-b04o5UDsSeiXhLSwNoYN0d3hbuG915u2qEy700c5PU0P1LhK26b5jBqI3tvUJ5t6b_NPgP8roPtnfWDfZ3JyfA</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Vijayakumar, Priyamvada ; Narayanan, Pritish ; Koren, Israel ; Mani Krishna, C. ; Moritz, Csaba Andras</creator><creatorcontrib>Vijayakumar, Priyamvada ; Narayanan, Pritish ; Koren, Israel ; Mani Krishna, C. ; Moritz, Csaba Andras</creatorcontrib><description>Reliable and scalable manufacturing of nanofabrics entails significant challenges. Scalable nanomanufacturing approaches that employ the use of lithographic masks in conjunction with nanofabrication based on self-assembly have been proposed. A bottom-up fabrication of nanoelectronic circuits is expected to be subject to various defects and identifying the types of defects that may occur during each step of a manufacturing pathway is essential in any attempt to achieve reliable manufacturing. The paper proposes a methodology for analyzing the sources of defects in a nano-manufacturing flow and estimating the resulting systematic yield loss. This methodology allows analyzing the impact of the fabrication process on the systematic yield. It integrates physical fabric considerations, manufacturing sequences and the resulting defect scenarios. This is in contrast to most current approaches that use conventional defect models and assume constant defect rates without analyzing the manufacturing pathway to determine the sources of defects and their probabilities (or rates). While the focus of the paper is on estimating the mask overlay-limited yield for the NASIC nano-fabric, the proposed approach can be easily adapted to suit other structured nano-fabrics.</description><identifier>ISSN: 2327-8218</identifier><identifier>ISBN: 1457709937</identifier><identifier>ISBN: 9781457709937</identifier><identifier>EISSN: 2327-8226</identifier><identifier>EISBN: 9781457709944</identifier><identifier>EISBN: 1457709945</identifier><identifier>EISBN: 9781457709951</identifier><identifier>EISBN: 1457709953</identifier><identifier>DOI: 10.1109/NANOARCH.2011.5941502</identifier><language>eng</language><publisher>Washington, DC, USA: IEEE Computer Society</publisher><subject>Applied computing -- Enterprise computing ; Applied computing -- Operations research -- Industry and manufacturing ; Applied computing -- Physical sciences and engineering -- Electronics ; CMOS integrated circuits ; Fabrics ; Manufacturing ; mask alignment ; mask offset ; Metals ; Nanoscale devices ; Nanowires ; overlay ; Systematics ; yield</subject><ispartof>2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011, p.181-188</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5941502$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,778,782,787,788,2054,27912,54907</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5941502$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Vijayakumar, Priyamvada</creatorcontrib><creatorcontrib>Narayanan, Pritish</creatorcontrib><creatorcontrib>Koren, Israel</creatorcontrib><creatorcontrib>Mani Krishna, C.</creatorcontrib><creatorcontrib>Moritz, Csaba Andras</creatorcontrib><title>Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics</title><title>2011 IEEE/ACM International Symposium on Nanoscale Architectures</title><addtitle>NANOARCH</addtitle><description>Reliable and scalable manufacturing of nanofabrics entails significant challenges. Scalable nanomanufacturing approaches that employ the use of lithographic masks in conjunction with nanofabrication based on self-assembly have been proposed. A bottom-up fabrication of nanoelectronic circuits is expected to be subject to various defects and identifying the types of defects that may occur during each step of a manufacturing pathway is essential in any attempt to achieve reliable manufacturing. The paper proposes a methodology for analyzing the sources of defects in a nano-manufacturing flow and estimating the resulting systematic yield loss. This methodology allows analyzing the impact of the fabrication process on the systematic yield. It integrates physical fabric considerations, manufacturing sequences and the resulting defect scenarios. This is in contrast to most current approaches that use conventional defect models and assume constant defect rates without analyzing the manufacturing pathway to determine the sources of defects and their probabilities (or rates). While the focus of the paper is on estimating the mask overlay-limited yield for the NASIC nano-fabric, the proposed approach can be easily adapted to suit other structured nano-fabrics.</description><subject>Applied computing -- Enterprise computing</subject><subject>Applied computing -- Operations research -- Industry and manufacturing</subject><subject>Applied computing -- Physical sciences and engineering -- Electronics</subject><subject>CMOS integrated circuits</subject><subject>Fabrics</subject><subject>Manufacturing</subject><subject>mask alignment</subject><subject>mask offset</subject><subject>Metals</subject><subject>Nanoscale devices</subject><subject>Nanowires</subject><subject>overlay</subject><subject>Systematics</subject><subject>yield</subject><issn>2327-8218</issn><issn>2327-8226</issn><isbn>1457709937</isbn><isbn>9781457709937</isbn><isbn>9781457709944</isbn><isbn>1457709945</isbn><isbn>9781457709951</isbn><isbn>1457709953</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNqVkNtKAzEQhuMJrLVPIEJeYNdMks0ml6VYWyitiF6HJE1kdQ9ls0X69m5tK946N8PwzT8wH0L3QFIAoh6W4-Vq_DKZpZQApJnikBF6hkYql8CzPCdKcX6OBpTRPJGUigt0cwIsv_wFIK_RKMYP0pcQiik5QM_zamNch5uAa1M3lam3oZ-3bVG_41A2X7ipcdzFzlemKxzeFb5c47KJ0Udc1D-h6EzpcTC2LVy8RVfBlNGPjn2I3qaPr5NZslg9zSfjRWIoVV0SmPCWgwNulKKOA10TZsFaySh1QkKeBQe-b04o5UDsSeiXhLSwNoYN0d3hbuG915u2qEy700c5PU0P1LhK26b5jBqI3tvUJ5t6b_NPgP8roPtnfWDfZ3JyfA</recordid><startdate>20110608</startdate><enddate>20110608</enddate><creator>Vijayakumar, Priyamvada</creator><creator>Narayanan, Pritish</creator><creator>Koren, Israel</creator><creator>Mani Krishna, C.</creator><creator>Moritz, Csaba Andras</creator><general>IEEE Computer Society</general><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>20110608</creationdate><title>Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics</title><author>Vijayakumar, Priyamvada ; Narayanan, Pritish ; Koren, Israel ; Mani Krishna, C. ; Moritz, Csaba Andras</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-a229t-f36eb41c14a992c412d03b1bb8322c68175fc1e175c699c16bb83f2d068b1daa3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Applied computing -- Enterprise computing</topic><topic>Applied computing -- Operations research -- Industry and manufacturing</topic><topic>Applied computing -- Physical sciences and engineering -- Electronics</topic><topic>CMOS integrated circuits</topic><topic>Fabrics</topic><topic>Manufacturing</topic><topic>mask alignment</topic><topic>mask offset</topic><topic>Metals</topic><topic>Nanoscale devices</topic><topic>Nanowires</topic><topic>overlay</topic><topic>Systematics</topic><topic>yield</topic><toplevel>online_resources</toplevel><creatorcontrib>Vijayakumar, Priyamvada</creatorcontrib><creatorcontrib>Narayanan, Pritish</creatorcontrib><creatorcontrib>Koren, Israel</creatorcontrib><creatorcontrib>Mani Krishna, C.</creatorcontrib><creatorcontrib>Moritz, Csaba Andras</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Vijayakumar, Priyamvada</au><au>Narayanan, Pritish</au><au>Koren, Israel</au><au>Mani Krishna, C.</au><au>Moritz, Csaba Andras</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics</atitle><btitle>2011 IEEE/ACM International Symposium on Nanoscale Architectures</btitle><stitle>NANOARCH</stitle><date>2011-06-08</date><risdate>2011</risdate><spage>181</spage><epage>188</epage><pages>181-188</pages><issn>2327-8218</issn><eissn>2327-8226</eissn><isbn>1457709937</isbn><isbn>9781457709937</isbn><eisbn>9781457709944</eisbn><eisbn>1457709945</eisbn><eisbn>9781457709951</eisbn><eisbn>1457709953</eisbn><abstract>Reliable and scalable manufacturing of nanofabrics entails significant challenges. Scalable nanomanufacturing approaches that employ the use of lithographic masks in conjunction with nanofabrication based on self-assembly have been proposed. A bottom-up fabrication of nanoelectronic circuits is expected to be subject to various defects and identifying the types of defects that may occur during each step of a manufacturing pathway is essential in any attempt to achieve reliable manufacturing. The paper proposes a methodology for analyzing the sources of defects in a nano-manufacturing flow and estimating the resulting systematic yield loss. This methodology allows analyzing the impact of the fabrication process on the systematic yield. It integrates physical fabric considerations, manufacturing sequences and the resulting defect scenarios. This is in contrast to most current approaches that use conventional defect models and assume constant defect rates without analyzing the manufacturing pathway to determine the sources of defects and their probabilities (or rates). While the focus of the paper is on estimating the mask overlay-limited yield for the NASIC nano-fabric, the proposed approach can be easily adapted to suit other structured nano-fabrics.</abstract><cop>Washington, DC, USA</cop><pub>IEEE Computer Society</pub><doi>10.1109/NANOARCH.2011.5941502</doi><tpages>8</tpages></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 2327-8218 |
ispartof | 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011, p.181-188 |
issn | 2327-8218 2327-8226 |
language | eng |
recordid | cdi_ieee_primary_5941502 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Applied computing -- Enterprise computing Applied computing -- Operations research -- Industry and manufacturing Applied computing -- Physical sciences and engineering -- Electronics CMOS integrated circuits Fabrics Manufacturing mask alignment mask offset Metals Nanoscale devices Nanowires overlay Systematics yield |
title | Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-15T17%3A10%3A09IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-acm_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Impact%20of%20nanomanufacturing%20flow%20on%20systematic%20yield%20losses%20in%20nanoscale%20fabrics&rft.btitle=2011%20IEEE/ACM%20International%20Symposium%20on%20Nanoscale%20Architectures&rft.au=Vijayakumar,%20Priyamvada&rft.date=2011-06-08&rft.spage=181&rft.epage=188&rft.pages=181-188&rft.issn=2327-8218&rft.eissn=2327-8226&rft.isbn=1457709937&rft.isbn_list=9781457709937&rft_id=info:doi/10.1109/NANOARCH.2011.5941502&rft_dat=%3Cacm_6IE%3Eacm_books_10_1109_NANOARCH_2011_5941502%3C/acm_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781457709944&rft.eisbn_list=1457709945&rft.eisbn_list=9781457709951&rft.eisbn_list=1457709953&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5941502&rfr_iscdi=true |