FPGA Implementation of an ASIP for high throughput DFT/DCT 1D/2D engine

In this paper, A novel architecture of an Application Specific Instruction Processor (ASIP) for scalable DFT/IDFT DCT/IDCT ID (N-point) and 2D (N × M point) engine is proposed. An in place configurable radix 2/3/4 butterfly, makes possible the implementation of two radix N/M is varied in the form of...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Hassan, Hanan M., Shalash, Ahmed F., Mohamed, Karim
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	ASIP and configurable HW Computer architecture DCT DFT Discrete cosine transforms Discrete Fourier transforms Engines Generators Process control Random access memory
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