Design of high-speed clock recovery circuit for burst-mode applications

This paper describes the architecture and design of high-speed clock recovery circuit for burst-mode applications. Since the proposed circuit is non-PLL-type and designed in fully digital style, it can provide faster acquisition time, better scalability and portability compared to PLL-type or analog...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Soojin Kim, Kyeongsoon Cho
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Clocks Delay Detectors Flip-flops Jitter Logic gates Synchronization
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