Optimizing Floating Point Units in Hybrid FPGAs
This paper introduces a methodology to optimize coarse-grained floating point units (FPUs) in a hybrid field-programmable gate array (FPGA), where the FPU consists of a number of interconnected floating point adders/subtracters (FAs), multipliers (FMs), and wordblocks (WBs). The wordblocks include r...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2012-07, Vol.20 (7), p.1295-1303 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
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| creator | ChiWai Yu Smith, A. M. Luk, W. Leong, P. H. W. Wilton, S. J. E. |
| description | This paper introduces a methodology to optimize coarse-grained floating point units (FPUs) in a hybrid field-programmable gate array (FPGA), where the FPU consists of a number of interconnected floating point adders/subtracters (FAs), multipliers (FMs), and wordblocks (WBs). The wordblocks include registers and lookup tables (LUTs) which can implement fixed point operations efficiently. We employ common subgraph extraction to determine the best mix of blocks within an FPU and study the area, speed and utilization tradeoff over a set of floating point benchmark circuits. We then explore the system impact of FPU density and flexibility in terms of area, speed, and routing resources. Finally, we derive an optimized coarse-grained FPU by considering both architectural and system-level issues. This proposed methodology can be used to evaluate a variety of FPU architecture optimizations. The results for the selected FPU architecture optimization show that although high density FPUs are slower, they have the advantages of improved area, area-delay product, and throughput. |
| doi_str_mv | 10.1109/TVLSI.2011.2153883 |
| format | Article |
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W.</creatorcontrib><creatorcontrib>Wilton, S. J. E.</creatorcontrib><title>Optimizing Floating Point Units in Hybrid FPGAs</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>This paper introduces a methodology to optimize coarse-grained floating point units (FPUs) in a hybrid field-programmable gate array (FPGA), where the FPU consists of a number of interconnected floating point adders/subtracters (FAs), multipliers (FMs), and wordblocks (WBs). The wordblocks include registers and lookup tables (LUTs) which can implement fixed point operations efficiently. We employ common subgraph extraction to determine the best mix of blocks within an FPU and study the area, speed and utilization tradeoff over a set of floating point benchmark circuits. We then explore the system impact of FPU density and flexibility in terms of area, speed, and routing resources. Finally, we derive an optimized coarse-grained FPU by considering both architectural and system-level issues. This proposed methodology can be used to evaluate a variety of FPU architecture optimizations. The results for the selected FPU architecture optimization show that although high density FPUs are slower, they have the advantages of improved area, area-delay product, and throughput.</description><subject>Applied sciences</subject><subject>Architecture</subject><subject>Benchmark testing</subject><subject>Circuit properties</subject><subject>Common subgraph extraction</subject><subject>Computer architecture</subject><subject>Density</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital circuits</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Field programmable gate arrays</subject><subject>field-programmable gate array (FPGA)</subject><subject>floating point (FP)</subject><subject>Floating point arithmetic</subject><subject>High density</subject><subject>Integrated circuits</subject><subject>Lookup tables</subject><subject>Merging</subject><subject>Methodology</subject><subject>Optimization</subject><subject>Routing</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Testing</topic><topic>Digital circuits</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Field programmable gate arrays</topic><topic>field-programmable gate array (FPGA)</topic><topic>floating point (FP)</topic><topic>Floating point arithmetic</topic><topic>High density</topic><topic>Integrated circuits</topic><topic>Lookup tables</topic><topic>Merging</topic><topic>Methodology</topic><topic>Optimization</topic><topic>Routing</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Studies</topic><topic>Very large scale integration</topic><topic>Wires</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>ChiWai Yu</creatorcontrib><creatorcontrib>Smith, A. M.</creatorcontrib><creatorcontrib>Luk, W.</creatorcontrib><creatorcontrib>Leong, P. H. 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E.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Optimizing Floating Point Units in Hybrid FPGAs</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2012-07-01</date><risdate>2012</risdate><volume>20</volume><issue>7</issue><spage>1295</spage><epage>1303</epage><pages>1295-1303</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>This paper introduces a methodology to optimize coarse-grained floating point units (FPUs) in a hybrid field-programmable gate array (FPGA), where the FPU consists of a number of interconnected floating point adders/subtracters (FAs), multipliers (FMs), and wordblocks (WBs). The wordblocks include registers and lookup tables (LUTs) which can implement fixed point operations efficiently. We employ common subgraph extraction to determine the best mix of blocks within an FPU and study the area, speed and utilization tradeoff over a set of floating point benchmark circuits. We then explore the system impact of FPU density and flexibility in terms of area, speed, and routing resources. Finally, we derive an optimized coarse-grained FPU by considering both architectural and system-level issues. This proposed methodology can be used to evaluate a variety of FPU architecture optimizations. The results for the selected FPU architecture optimization show that although high density FPUs are slower, they have the advantages of improved area, area-delay product, and throughput.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2011.2153883</doi><tpages>9</tpages><oa>free_for_read</oa></addata></record> |
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| subjects | Applied sciences Architecture Benchmark testing Circuit properties Common subgraph extraction Computer architecture Density Design. Technologies. Operation analysis. Testing Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Field programmable gate arrays field-programmable gate array (FPGA) floating point (FP) Floating point arithmetic High density Integrated circuits Lookup tables Merging Methodology Optimization Routing Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Studies Very large scale integration Wires |
| title | Optimizing Floating Point Units in Hybrid FPGAs |
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