Self-heating analysis of power MOSFET module during burn-in test

Self-heating analysis of power MOSFET module during burn-in test

The paper deals with the thermal behavior for paralleled MOSFET's module during accelerated cycling burn-in test in harsh ambient and current conditions. The aim of the work is to optimize the key parameters acting on the self-heating in order to avoid undesirable failures resulting from overhe...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Stefanov, E. N., Escoffier, R., Blondel, G., Rouleau, B.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Computer architecture
Heating
Logic gates
Power MOSFET
Predictive models
Temperature measurement
Wires
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 371
container_issue
container_start_page 368
container_title
container_volume
creator Stefanov, E. N.
Escoffier, R.
Blondel, G.
Rouleau, B.
description The paper deals with the thermal behavior for paralleled MOSFET's module during accelerated cycling burn-in test in harsh ambient and current conditions. The aim of the work is to optimize the key parameters acting on the self-heating in order to avoid undesirable failures resulting from overheating. An electro-thermal model is developed to simulate the device temperature during the test. Well calibrated to the experimental data for R on and avalanche phases, our model allowed realistic thermal prediction. The impact of gate bias, pulse time, as well as disparities of breakdown voltage between the FETs was analyzed and the test conditions were optimized.
doi_str_mv 10.1109/ISPSD.2011.5890867
format Conference Proceeding
fullrecord <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5890867</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5890867</ieee_id><sourcerecordid>5890867</sourcerecordid><originalsourceid>FETCH-LOGICAL-i175t-28132e3b065d277d7783c1892b5f2b1b7dd60a5ac4a4aeede92cd15471c303033</originalsourceid><addsrcrecordid>eNpVUMlOwzAUNJtEVfIDcPEPOPh59w1UClQqKlLgXDnxCwSlSZVFqH9PEL0wc5jDLIch5Bp4CsD97Sp7zR5SwQFS7Tx3xp6QxFsHSijllJDilMzAK8P4FDr752lzPnncSGacVpck6fsvPsEYr7mbkbsM65J9Yhiq5oOGJtSHvuppW9J9-40dfdlkj8s3umvjWCONY_cby8euYVVDB-yHK3JRhrrH5Khz8j4VFs9svXlaLe7XrAKrByYcSIEy50ZHYW201skCnBe5LkUOuY3R8KBDoYIKiBG9KCJoZaGQfKKck5u_3QoRt_uu2oXusD3-IX8Alx9OHQ</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Self-heating analysis of power MOSFET module during burn-in test</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Stefanov, E. N. ; Escoffier, R. ; Blondel, G. ; Rouleau, B.</creator><creatorcontrib>Stefanov, E. N. ; Escoffier, R. ; Blondel, G. ; Rouleau, B.</creatorcontrib><description>The paper deals with the thermal behavior for paralleled MOSFET's module during accelerated cycling burn-in test in harsh ambient and current conditions. The aim of the work is to optimize the key parameters acting on the self-heating in order to avoid undesirable failures resulting from overheating. An electro-thermal model is developed to simulate the device temperature during the test. Well calibrated to the experimental data for R on and avalanche phases, our model allowed realistic thermal prediction. The impact of gate bias, pulse time, as well as disparities of breakdown voltage between the FETs was analyzed and the test conditions were optimized.</description><identifier>ISSN: 1063-6854</identifier><identifier>ISBN: 9781424484256</identifier><identifier>ISBN: 1424484251</identifier><identifier>EISSN: 1946-0201</identifier><identifier>EISBN: 9781424484232</identifier><identifier>EISBN: 1424484243</identifier><identifier>EISBN: 1424484235</identifier><identifier>EISBN: 9781424484249</identifier><identifier>DOI: 10.1109/ISPSD.2011.5890867</identifier><language>eng</language><publisher>IEEE</publisher><subject>Computer architecture ; Heating ; Logic gates ; Power MOSFET ; Predictive models ; Temperature measurement ; Wires</subject><ispartof>2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs, 2011, p.368-371</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5890867$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5890867$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Stefanov, E. N.</creatorcontrib><creatorcontrib>Escoffier, R.</creatorcontrib><creatorcontrib>Blondel, G.</creatorcontrib><creatorcontrib>Rouleau, B.</creatorcontrib><title>Self-heating analysis of power MOSFET module during burn-in test</title><title>2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs</title><addtitle>ISPSD</addtitle><description>The paper deals with the thermal behavior for paralleled MOSFET's module during accelerated cycling burn-in test in harsh ambient and current conditions. The aim of the work is to optimize the key parameters acting on the self-heating in order to avoid undesirable failures resulting from overheating. An electro-thermal model is developed to simulate the device temperature during the test. Well calibrated to the experimental data for R on and avalanche phases, our model allowed realistic thermal prediction. The impact of gate bias, pulse time, as well as disparities of breakdown voltage between the FETs was analyzed and the test conditions were optimized.</description><subject>Computer architecture</subject><subject>Heating</subject><subject>Logic gates</subject><subject>Power MOSFET</subject><subject>Predictive models</subject><subject>Temperature measurement</subject><subject>Wires</subject><issn>1063-6854</issn><issn>1946-0201</issn><isbn>9781424484256</isbn><isbn>1424484251</isbn><isbn>9781424484232</isbn><isbn>1424484243</isbn><isbn>1424484235</isbn><isbn>9781424484249</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVUMlOwzAUNJtEVfIDcPEPOPh59w1UClQqKlLgXDnxCwSlSZVFqH9PEL0wc5jDLIch5Bp4CsD97Sp7zR5SwQFS7Tx3xp6QxFsHSijllJDilMzAK8P4FDr752lzPnncSGacVpck6fsvPsEYr7mbkbsM65J9Yhiq5oOGJtSHvuppW9J9-40dfdlkj8s3umvjWCONY_cby8euYVVDB-yHK3JRhrrH5Khz8j4VFs9svXlaLe7XrAKrByYcSIEy50ZHYW201skCnBe5LkUOuY3R8KBDoYIKiBG9KCJoZaGQfKKck5u_3QoRt_uu2oXusD3-IX8Alx9OHQ</recordid><startdate>201105</startdate><enddate>201105</enddate><creator>Stefanov, E. N.</creator><creator>Escoffier, R.</creator><creator>Blondel, G.</creator><creator>Rouleau, B.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201105</creationdate><title>Self-heating analysis of power MOSFET module during burn-in test</title><author>Stefanov, E. N. ; Escoffier, R. ; Blondel, G. ; Rouleau, B.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-28132e3b065d277d7783c1892b5f2b1b7dd60a5ac4a4aeede92cd15471c303033</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Computer architecture</topic><topic>Heating</topic><topic>Logic gates</topic><topic>Power MOSFET</topic><topic>Predictive models</topic><topic>Temperature measurement</topic><topic>Wires</topic><toplevel>online_resources</toplevel><creatorcontrib>Stefanov, E. N.</creatorcontrib><creatorcontrib>Escoffier, R.</creatorcontrib><creatorcontrib>Blondel, G.</creatorcontrib><creatorcontrib>Rouleau, B.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Stefanov, E. N.</au><au>Escoffier, R.</au><au>Blondel, G.</au><au>Rouleau, B.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Self-heating analysis of power MOSFET module during burn-in test</atitle><btitle>2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs</btitle><stitle>ISPSD</stitle><date>2011-05</date><risdate>2011</risdate><spage>368</spage><epage>371</epage><pages>368-371</pages><issn>1063-6854</issn><eissn>1946-0201</eissn><isbn>9781424484256</isbn><isbn>1424484251</isbn><eisbn>9781424484232</eisbn><eisbn>1424484243</eisbn><eisbn>1424484235</eisbn><eisbn>9781424484249</eisbn><abstract>The paper deals with the thermal behavior for paralleled MOSFET's module during accelerated cycling burn-in test in harsh ambient and current conditions. The aim of the work is to optimize the key parameters acting on the self-heating in order to avoid undesirable failures resulting from overheating. An electro-thermal model is developed to simulate the device temperature during the test. Well calibrated to the experimental data for R on and avalanche phases, our model allowed realistic thermal prediction. The impact of gate bias, pulse time, as well as disparities of breakdown voltage between the FETs was analyzed and the test conditions were optimized.</abstract><pub>IEEE</pub><doi>10.1109/ISPSD.2011.5890867</doi><tpages>4</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 1063-6854
ispartof 2011 IEEE 23rd International Symposium on Power Semiconductor Devices and ICs, 2011, p.368-371
issn 1063-6854
1946-0201
language eng
recordid cdi_ieee_primary_5890867
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Computer architecture
Heating
Logic gates
Power MOSFET
Predictive models
Temperature measurement
Wires
title Self-heating analysis of power MOSFET module during burn-in test
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-23T11%3A29%3A54IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Self-heating%20analysis%20of%20power%20MOSFET%20module%20during%20burn-in%20test&rft.btitle=2011%20IEEE%2023rd%20International%20Symposium%20on%20Power%20Semiconductor%20Devices%20and%20ICs&rft.au=Stefanov,%20E.%20N.&rft.date=2011-05&rft.spage=368&rft.epage=371&rft.pages=368-371&rft.issn=1063-6854&rft.eissn=1946-0201&rft.isbn=9781424484256&rft.isbn_list=1424484251&rft_id=info:doi/10.1109/ISPSD.2011.5890867&rft_dat=%3Cieee_6IE%3E5890867%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424484232&rft.eisbn_list=1424484243&rft.eisbn_list=1424484235&rft.eisbn_list=9781424484249&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5890867&rfr_iscdi=true