A 250 MHz 5 W RISC microprocessor with on-chip L2 cache controller

This superscalar microprocessor is a 32b implementation of the PowerPC Architecture(TM) specification based on a micro-architecture designed for high performance and low power. Two instructions per cycle can be dispatched in this superscalar design. The processor includes dual 32kB 8-way instruction...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Reed, P., Alexander, M., Alvarez, J., Brauer, M., Chai-Chin Chao, Croxton, C., Eisen, L., Toan Le, Tai Ngo, Nicoletta, C., Sanchez, H., Taylor, S., Vanderschaaf, N., Gerosa, G.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Chaos Clocks Energy management Frequency estimation Microprocessors Phase locked loops Pipelines Power system management Reduced instruction set computing Thermal management
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