A 250 MHz 5 W RISC microprocessor with on-chip L2 cache controller
This superscalar microprocessor is a 32b implementation of the PowerPC Architecture(TM) specification based on a micro-architecture designed for high performance and low power. Two instructions per cycle can be dispatched in this superscalar design. The processor includes dual 32kB 8-way instruction...
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| creator | Reed, P. Alexander, M. Alvarez, J. Brauer, M. Chai-Chin Chao Croxton, C. Eisen, L. Toan Le Tai Ngo Nicoletta, C. Sanchez, H. Taylor, S. Vanderschaaf, N. Gerosa, G. |
| description | This superscalar microprocessor is a 32b implementation of the PowerPC Architecture(TM) specification based on a micro-architecture designed for high performance and low power. Two instructions per cycle can be dispatched in this superscalar design. The processor includes dual 32kB 8-way instruction and data caches, a floating-point unit, two integer units, a branch unit, a load/store unit, and a system unit. An L2 tag and cache controller with a dedicated L2 bus interface are added to provide a low-cost L2 cache solution using commodity SRAMs for the data. |
| doi_str_mv | 10.1109/ISSCC.1997.585463 |
| format | Conference Proceeding |
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Digest of Technical Papers</btitle><stitle>ISSCC</stitle><date>1997-01-01</date><risdate>1997</risdate><volume>40</volume><spage>412</spage><epage>413</epage><pages>412-413</pages><issn>0193-6530</issn><eissn>2376-8606</eissn><isbn>9780780337213</isbn><isbn>0780337212</isbn><abstract>This superscalar microprocessor is a 32b implementation of the PowerPC Architecture(TM) specification based on a micro-architecture designed for high performance and low power. Two instructions per cycle can be dispatched in this superscalar design. The processor includes dual 32kB 8-way instruction and data caches, a floating-point unit, two integer units, a branch unit, a load/store unit, and a system unit. An L2 tag and cache controller with a dedicated L2 bus interface are added to provide a low-cost L2 cache solution using commodity SRAMs for the data.</abstract><pub>IEEE</pub><doi>10.1109/ISSCC.1997.585463</doi><tpages>2</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0193-6530 |
| ispartof | 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers, 1997, Vol.40, p.412-413 |
| issn | 0193-6530 2376-8606 |
| language | eng |
| recordid | cdi_ieee_primary_585463 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Chaos Clocks Energy management Frequency estimation Microprocessors Phase locked loops Pipelines Power system management Reduced instruction set computing Thermal management |
| title | A 250 MHz 5 W RISC microprocessor with on-chip L2 cache controller |
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