The impact of stochastic dopant and interconnect distributions on gigascale integration
Opportunities for GSI are governed by a hierarchy of physical limits whose five levels can be codified as: fundamental, material, device, circuit, and system. This distinctive methodology is extended here by elucidating the impact on GSI of random dopant atom placement in the channel region of a MOS...
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creator | Meindl, J.D. De, V.K. Wills, D.S. Eble, J.C. Xinghai Tang Davis, J.A. Austin, B. Bhavnagarwala, A.J. |
description | Opportunities for GSI are governed by a hierarchy of physical limits whose five levels can be codified as: fundamental, material, device, circuit, and system. This distinctive methodology is extended here by elucidating the impact on GSI of random dopant atom placement in the channel region of a MOSFET and of interconnect distributions in random logic networks in context with projected advances in device and circuit techniques. |
doi_str_mv | 10.1109/ISSCC.1997.585366 |
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fullrecord | <record><control><sourceid>proquest_6IE</sourceid><recordid>TN_cdi_ieee_primary_585366</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>585366</ieee_id><sourcerecordid>26615545</sourcerecordid><originalsourceid>FETCH-LOGICAL-i203t-69da1df862edb9fba23fba37205604b56552cc599e304b1a53dbc71e060a17893</originalsourceid><addsrcrecordid>eNotkEtPwzAQhC0eEqX0B8DJJ24p67h24iOKeFSqxKFFHKON7bRGqR1i58C_J1Ck1Y5G82k1WkJuGSwZA_Ww3m6rasmUKpaiFFzKMzLLeSGzUoI8JwtVlDAN50XO-AWZAVM8k4LDFbmO8RMAhJLljHzsDpa6Y4860dDSmII-YExOUxN69ImiN9T5ZAcdvLcTZVxMg2vG5IKPNHi6d3uMGjv7x-0H_E1uyGWLXbSLf52T9-enXfWabd5e1tXjJnM58JRJZZCZtpS5NY1qG8z5tKbSICSsGiGFyLUWSlk-WYaCm0YXzIIEZEWp-Jzcn-72Q_gabUz10UVtuw69DWOscymZECsxgXcn0Flr635wRxy-69Pv-A-SxWIL</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype><pqid>26615545</pqid></control><display><type>conference_proceeding</type><title>The impact of stochastic dopant and interconnect distributions on gigascale integration</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Meindl, J.D. ; De, V.K. ; Wills, D.S. ; Eble, J.C. ; Xinghai Tang ; Davis, J.A. ; Austin, B. ; Bhavnagarwala, A.J.</creator><creatorcontrib>Meindl, J.D. ; De, V.K. ; Wills, D.S. ; Eble, J.C. ; Xinghai Tang ; Davis, J.A. ; Austin, B. ; Bhavnagarwala, A.J.</creatorcontrib><description>Opportunities for GSI are governed by a hierarchy of physical limits whose five levels can be codified as: fundamental, material, device, circuit, and system. This distinctive methodology is extended here by elucidating the impact on GSI of random dopant atom placement in the channel region of a MOSFET and of interconnect distributions in random logic networks in context with projected advances in device and circuit techniques.</description><identifier>ISSN: 0193-6530</identifier><identifier>ISBN: 9780780337213</identifier><identifier>ISBN: 0780337212</identifier><identifier>EISSN: 2376-8606</identifier><identifier>DOI: 10.1109/ISSCC.1997.585366</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit simulation ; CMOS logic circuits ; CMOS technology ; Doping profiles ; Integrated circuit interconnections ; Logic circuits ; Logic devices ; MOSFET circuits ; Stochastic processes ; Threshold voltage</subject><ispartof>1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers, 1997, Vol.40, p.232-233</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/585366$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/585366$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Meindl, J.D.</creatorcontrib><creatorcontrib>De, V.K.</creatorcontrib><creatorcontrib>Wills, D.S.</creatorcontrib><creatorcontrib>Eble, J.C.</creatorcontrib><creatorcontrib>Xinghai Tang</creatorcontrib><creatorcontrib>Davis, J.A.</creatorcontrib><creatorcontrib>Austin, B.</creatorcontrib><creatorcontrib>Bhavnagarwala, A.J.</creatorcontrib><title>The impact of stochastic dopant and interconnect distributions on gigascale integration</title><title>1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers</title><addtitle>ISSCC</addtitle><description>Opportunities for GSI are governed by a hierarchy of physical limits whose five levels can be codified as: fundamental, material, device, circuit, and system. This distinctive methodology is extended here by elucidating the impact on GSI of random dopant atom placement in the channel region of a MOSFET and of interconnect distributions in random logic networks in context with projected advances in device and circuit techniques.</description><subject>Circuit simulation</subject><subject>CMOS logic circuits</subject><subject>CMOS technology</subject><subject>Doping profiles</subject><subject>Integrated circuit interconnections</subject><subject>Logic circuits</subject><subject>Logic devices</subject><subject>MOSFET circuits</subject><subject>Stochastic processes</subject><subject>Threshold voltage</subject><issn>0193-6530</issn><issn>2376-8606</issn><isbn>9780780337213</isbn><isbn>0780337212</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1997</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkEtPwzAQhC0eEqX0B8DJJ24p67h24iOKeFSqxKFFHKON7bRGqR1i58C_J1Ck1Y5G82k1WkJuGSwZA_Ww3m6rasmUKpaiFFzKMzLLeSGzUoI8JwtVlDAN50XO-AWZAVM8k4LDFbmO8RMAhJLljHzsDpa6Y4860dDSmII-YExOUxN69ImiN9T5ZAcdvLcTZVxMg2vG5IKPNHi6d3uMGjv7x-0H_E1uyGWLXbSLf52T9-enXfWabd5e1tXjJnM58JRJZZCZtpS5NY1qG8z5tKbSICSsGiGFyLUWSlk-WYaCm0YXzIIEZEWp-Jzcn-72Q_gabUz10UVtuw69DWOscymZECsxgXcn0Flr635wRxy-69Pv-A-SxWIL</recordid><startdate>19970101</startdate><enddate>19970101</enddate><creator>Meindl, J.D.</creator><creator>De, V.K.</creator><creator>Wills, D.S.</creator><creator>Eble, J.C.</creator><creator>Xinghai Tang</creator><creator>Davis, J.A.</creator><creator>Austin, B.</creator><creator>Bhavnagarwala, A.J.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope><scope>7SC</scope><scope>7U5</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>19970101</creationdate><title>The impact of stochastic dopant and interconnect distributions on gigascale integration</title><author>Meindl, J.D. ; De, V.K. ; Wills, D.S. ; Eble, J.C. ; Xinghai Tang ; Davis, J.A. ; Austin, B. ; Bhavnagarwala, A.J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i203t-69da1df862edb9fba23fba37205604b56552cc599e304b1a53dbc71e060a17893</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1997</creationdate><topic>Circuit simulation</topic><topic>CMOS logic circuits</topic><topic>CMOS technology</topic><topic>Doping profiles</topic><topic>Integrated circuit interconnections</topic><topic>Logic circuits</topic><topic>Logic devices</topic><topic>MOSFET circuits</topic><topic>Stochastic processes</topic><topic>Threshold voltage</topic><toplevel>online_resources</toplevel><creatorcontrib>Meindl, J.D.</creatorcontrib><creatorcontrib>De, V.K.</creatorcontrib><creatorcontrib>Wills, D.S.</creatorcontrib><creatorcontrib>Eble, J.C.</creatorcontrib><creatorcontrib>Xinghai Tang</creatorcontrib><creatorcontrib>Davis, J.A.</creatorcontrib><creatorcontrib>Austin, B.</creatorcontrib><creatorcontrib>Bhavnagarwala, A.J.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection><collection>Computer and Information Systems Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Meindl, J.D.</au><au>De, V.K.</au><au>Wills, D.S.</au><au>Eble, J.C.</au><au>Xinghai Tang</au><au>Davis, J.A.</au><au>Austin, B.</au><au>Bhavnagarwala, A.J.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>The impact of stochastic dopant and interconnect distributions on gigascale integration</atitle><btitle>1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers</btitle><stitle>ISSCC</stitle><date>1997-01-01</date><risdate>1997</risdate><volume>40</volume><spage>232</spage><epage>233</epage><pages>232-233</pages><issn>0193-6530</issn><eissn>2376-8606</eissn><isbn>9780780337213</isbn><isbn>0780337212</isbn><abstract>Opportunities for GSI are governed by a hierarchy of physical limits whose five levels can be codified as: fundamental, material, device, circuit, and system. This distinctive methodology is extended here by elucidating the impact on GSI of random dopant atom placement in the channel region of a MOSFET and of interconnect distributions in random logic networks in context with projected advances in device and circuit techniques.</abstract><pub>IEEE</pub><doi>10.1109/ISSCC.1997.585366</doi><tpages>2</tpages></addata></record> |
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identifier | ISSN: 0193-6530 |
ispartof | 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers, 1997, Vol.40, p.232-233 |
issn | 0193-6530 2376-8606 |
language | eng |
recordid | cdi_ieee_primary_585366 |
source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Circuit simulation CMOS logic circuits CMOS technology Doping profiles Integrated circuit interconnections Logic circuits Logic devices MOSFET circuits Stochastic processes Threshold voltage |
title | The impact of stochastic dopant and interconnect distributions on gigascale integration |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-30T03%3A20%3A15IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=The%20impact%20of%20stochastic%20dopant%20and%20interconnect%20distributions%20on%20gigascale%20integration&rft.btitle=1997%20IEEE%20International%20Solids-State%20Circuits%20Conference.%20Digest%20of%20Technical%20Papers&rft.au=Meindl,%20J.D.&rft.date=1997-01-01&rft.volume=40&rft.spage=232&rft.epage=233&rft.pages=232-233&rft.issn=0193-6530&rft.eissn=2376-8606&rft.isbn=9780780337213&rft.isbn_list=0780337212&rft_id=info:doi/10.1109/ISSCC.1997.585366&rft_dat=%3Cproquest_6IE%3E26615545%3C/proquest_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=26615545&rft_id=info:pmid/&rft_ieee_id=585366&rfr_iscdi=true |