Implementation issues for congestion control in ATM networks
The design of Broadband Integrated Services Digital Networks (B-ISDN) requires the investigation of specific techniques to guarantee different Quality of Services (QoS) requirements for each traffic class in the network. In this context, a unified environment for the simulation and design of an ATM...
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| creator | Marchese, M. Curatelli, F. Chirico, M. Mangeruca, L. |
| description | The design of Broadband Integrated Services Digital Networks (B-ISDN) requires the investigation of specific techniques to guarantee different Quality of Services (QoS) requirements for each traffic class in the network. In this context, a unified environment for the simulation and design of an ATM node is a useful approach to test the effectiveness and the implementation aspects of the techniques mentioned above. In this paper a complete ATM node has been modelled in VHDL in a modular and flexible way and critical computational aspects are investigated. |
| doi_str_mv | 10.1109/ICECS.1996.584480 |
| format | Conference Proceeding |
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In this context, a unified environment for the simulation and design of an ATM node is a useful approach to test the effectiveness and the implementation aspects of the techniques mentioned above. In this paper a complete ATM node has been modelled in VHDL in a modular and flexible way and critical computational aspects are investigated.</description><identifier>ISBN: 9780780336506</identifier><identifier>ISBN: 078033650X</identifier><identifier>DOI: 10.1109/ICECS.1996.584480</identifier><language>eng</language><publisher>IEEE</publisher><subject>Admission control ; Asynchronous transfer mode ; B-ISDN ; Computational modeling ; Control systems ; Intelligent networks ; Quality of service ; Scheduling ; Telecommunication computing ; Traffic control</subject><ispartof>Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996, Vol.2, p.788-791 vol.2</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/584480$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,4035,4036,27904,54898</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/584480$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Marchese, M.</creatorcontrib><creatorcontrib>Curatelli, F.</creatorcontrib><creatorcontrib>Chirico, M.</creatorcontrib><creatorcontrib>Mangeruca, L.</creatorcontrib><title>Implementation issues for congestion control in ATM networks</title><title>Proceedings of Third International Conference on Electronics, Circuits, and Systems</title><addtitle>ICECS</addtitle><description>The design of Broadband Integrated Services Digital Networks (B-ISDN) requires the investigation of specific techniques to guarantee different Quality of Services (QoS) requirements for each traffic class in the network. In this context, a unified environment for the simulation and design of an ATM node is a useful approach to test the effectiveness and the implementation aspects of the techniques mentioned above. In this paper a complete ATM node has been modelled in VHDL in a modular and flexible way and critical computational aspects are investigated.</description><subject>Admission control</subject><subject>Asynchronous transfer mode</subject><subject>B-ISDN</subject><subject>Computational modeling</subject><subject>Control systems</subject><subject>Intelligent networks</subject><subject>Quality of service</subject><subject>Scheduling</subject><subject>Telecommunication computing</subject><subject>Traffic control</subject><isbn>9780780336506</isbn><isbn>078033650X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1996</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotT81KAzEYDIhQqfsA9ZQX2DVp_sFLWaouVDxYzyW7_SLR3aQkEfHtXWyHGWb4Dt8wCK0oaSgl5r5rt-1bQ42RjdCca3KFKqM0mcmYFEQuUJXzJ5nBOTNrc4Meuuk0wgSh2OJjwD7nb8jYxYSHGD4g_1_nWFIcsQ94s3_BAcpPTF_5Fl07O2aoLr5E74_bfftc716funazqz0lvNTmqAzla-Eon3uF5EIZ0g98FtEMFANmnXIAVhPbK816GI5Wg9TG9pJbtkR3578eAA6n5Cebfg_niewPPslHSQ</recordid><startdate>1996</startdate><enddate>1996</enddate><creator>Marchese, M.</creator><creator>Curatelli, F.</creator><creator>Chirico, M.</creator><creator>Mangeruca, L.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1996</creationdate><title>Implementation issues for congestion control in ATM networks</title><author>Marchese, M. ; Curatelli, F. ; Chirico, M. ; Mangeruca, L.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i104t-9d791425f140445645790bc40bc083e73e3af7feea80ab783becda8e689ab64a3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1996</creationdate><topic>Admission control</topic><topic>Asynchronous transfer mode</topic><topic>B-ISDN</topic><topic>Computational modeling</topic><topic>Control systems</topic><topic>Intelligent networks</topic><topic>Quality of service</topic><topic>Scheduling</topic><topic>Telecommunication computing</topic><topic>Traffic control</topic><toplevel>online_resources</toplevel><creatorcontrib>Marchese, M.</creatorcontrib><creatorcontrib>Curatelli, F.</creatorcontrib><creatorcontrib>Chirico, M.</creatorcontrib><creatorcontrib>Mangeruca, L.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Marchese, M.</au><au>Curatelli, F.</au><au>Chirico, M.</au><au>Mangeruca, L.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Implementation issues for congestion control in ATM networks</atitle><btitle>Proceedings of Third International Conference on Electronics, Circuits, and Systems</btitle><stitle>ICECS</stitle><date>1996</date><risdate>1996</risdate><volume>2</volume><spage>788</spage><epage>791 vol.2</epage><pages>788-791 vol.2</pages><isbn>9780780336506</isbn><isbn>078033650X</isbn><abstract>The design of Broadband Integrated Services Digital Networks (B-ISDN) requires the investigation of specific techniques to guarantee different Quality of Services (QoS) requirements for each traffic class in the network. In this context, a unified environment for the simulation and design of an ATM node is a useful approach to test the effectiveness and the implementation aspects of the techniques mentioned above. In this paper a complete ATM node has been modelled in VHDL in a modular and flexible way and critical computational aspects are investigated.</abstract><pub>IEEE</pub><doi>10.1109/ICECS.1996.584480</doi></addata></record> |
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| identifier | ISBN: 9780780336506 |
| ispartof | Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996, Vol.2, p.788-791 vol.2 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Admission control Asynchronous transfer mode B-ISDN Computational modeling Control systems Intelligent networks Quality of service Scheduling Telecommunication computing Traffic control |
| title | Implementation issues for congestion control in ATM networks |
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