Performance driven placement for cell-based designs
In this paper we present a performance driven quadratic programming based placement method for large ASICs. A set of performance bounds is first calculated for a given circuit. The performance bounds are calculated using a zero-slack algorithm. The performance bounds are then used to derive a timing...
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| creator | Natesan, V. Bhatia, D. |
| description | In this paper we present a performance driven quadratic programming based placement method for large ASICs. A set of performance bounds is first calculated for a given circuit. The performance bounds are calculated using a zero-slack algorithm. The performance bounds are then used to derive a timing driven placement for cell based layouts. The bounds, if satisfied, guarantee correct operation of circuit for specified timing requirements. The approach has been integrated with high-level synthesis tools for generating layouts of datapaths of synthesized designs. |
| doi_str_mv | 10.1109/ASIC.1995.580722 |
| format | Conference Proceeding |
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A set of performance bounds is first calculated for a given circuit. The performance bounds are calculated using a zero-slack algorithm. The performance bounds are then used to derive a timing driven placement for cell based layouts. The bounds, if satisfied, guarantee correct operation of circuit for specified timing requirements. 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A set of performance bounds is first calculated for a given circuit. The performance bounds are calculated using a zero-slack algorithm. The performance bounds are then used to derive a timing driven placement for cell based layouts. The bounds, if satisfied, guarantee correct operation of circuit for specified timing requirements. The approach has been integrated with high-level synthesis tools for generating layouts of datapaths of synthesized designs.</abstract><pub>IEEE</pub><doi>10.1109/ASIC.1995.580722</doi><tpages>4</tpages></addata></record> |
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| identifier | ISSN: 1063-0988 |
| ispartof | Proceedings of Eighth International Application Specific Integrated Circuits Conference, 1995, p.237-240 |
| issn | 1063-0988 2164-1773 |
| language | eng |
| recordid | cdi_ieee_primary_580722 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Contracts Design automation Feedback High level synthesis Integrated circuit synthesis Laboratories Quadratic programming Solid state circuits Timing Workability |
| title | Performance driven placement for cell-based designs |
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