BER estimation for MIMO HSDPA : Chip level Wiener equalizer and successive interference cancellation

In this paper we describe and simulate an accurate Bit Error Rate (BER) estimator for a chip level Wiener equalizer and combined equalizer/interference canceller for employment with the CDMA MIMO High Speed Downlink Packet Access (HSDPA) feature of the Third Generation Partnership Project (3GPP). In...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Yongwoo Lee, Voltz, P, Pietraski, P, Rui Yang
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Bit error rate Equalizers Interference cancellation MIMO Multiaccess communication Receivers
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!