Low Coverage Analysis using dynamic un-testability debug in ATPG
In this paper, we propose an automated technique to identify the reasons for un-testable faults and, an interactive Low Coverage Analysis flow to expedite the coverage analysis step, in scan ATPG. We seamlessly use an implication graph to keep track of the reasons that are responsible for each confl...
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| creator | Chandrasekar, K Bommu, S Sengupta, S |
| description | In this paper, we propose an automated technique to identify the reasons for un-testable faults and, an interactive Low Coverage Analysis flow to expedite the coverage analysis step, in scan ATPG. We seamlessly use an implication graph to keep track of the reasons that are responsible for each conflict encountered during ATPG. As ATPG progresses, for each fault, all the reasons arising from ATPG constraints are logged systematically. Then, we use a low coverage analysis flow to cumulatively analyze the faults and reasons / ATPG constraints. We integrated the proposed technique into the production scan ATPG flow at Intel. The proposed technique resolved up to 15% coverage gap on real micro-processor designs in a few hours. Potentially, this would have, otherwise, taken a few days of manual effort with considerable design knowledge. |
| doi_str_mv | 10.1109/VTS.2011.5783736 |
| format | Conference Proceeding |
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| ispartof | 29th VLSI Test Symposium, 2011, p.291-296 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Algorithm design and analysis Automatic test pattern generation Circuit faults Cognition Fault diagnosis Logic gates Very large scale integration |
| title | Low Coverage Analysis using dynamic un-testability debug in ATPG |
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