Low-jitter code-jumping for all-digital PLL to support almost continuous frequency tracking
We present a fully cell-based All-Digital Phase-Locked Loop (ADPLL) with almost continuous tracking range of frequency. Using TSMC 0.18μm CMOS technology, this test chip can operate from 91.6MHz to 1.173GHz with an average resolution of 2.1ps. It features a new Mirror-DCO-Based Calibration Mechanism...
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| creator | Pei-Ying Chao Chao-Wen Tzeng Shan-Chien Fang Chia-Chien Weng Shi-Yu Huang |
| description | We present a fully cell-based All-Digital Phase-Locked Loop (ADPLL) with almost continuous tracking range of frequency. Using TSMC 0.18μm CMOS technology, this test chip can operate from 91.6MHz to 1.173GHz with an average resolution of 2.1ps. It features a new Mirror-DCO-Based Calibration Mechanism that enables smooth code-jumping to mitigate the segmented clock-period profile problem faced by most ADPLL's. This mechanism can suppress the jitter significantly when there is temperature and/or power supply variation during operation. This design has been validated in 0.18um CMOS technology. Measurement results show that when operating at 1GHz, the RMS jitter is 2.5ps and the peak-to-peak jitter is 15.3ps, respectively. |
| doi_str_mv | 10.1109/VDAT.2011.5783612 |
| format | Conference Proceeding |
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| fulltext | fulltext_linktorsrc |
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| ispartof | Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, 2011, p.1-4 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | All-Digital Phase-Locked Loop (ADPLL) Calibration Clocks CMOS integrated circuits Digitally Controlled Oscillator (DCO) Frequency control Jitter Mirrors Phase locked loops smooth-code jumping |
| title | Low-jitter code-jumping for all-digital PLL to support almost continuous frequency tracking |
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