Statistical analysis of 6T SRAM data retention voltage under process variation
One of the main issues in scaled SRAMs is the increase in static power. A common way to reduce the static power consumption of an SRAM array is to decrease its supply voltage when in memory retention mode. Decreasing the supply voltage however has a strong negative effect on the stability of the SRA...
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| creator | Vatajelu, Elena I. Figueras, Joan |
| description | One of the main issues in scaled SRAMs is the increase in static power. A common way to reduce the static power consumption of an SRAM array is to decrease its supply voltage when in memory retention mode. Decreasing the supply voltage however has a strong negative effect on the stability of the SRAM cell. This paper statistically analyzes the behavior of the 6T SRAM cell in data retention mode, under process variability. The failure probabilities under various supply voltages are determined for different technology nodes, and the Data Retention Voltage is determined. For the 45nm PTM SRAM cell under random threshold voltage variation, the Data Retention Voltage is found to be 423mV while for the 16nm PTM SRAM, the DRV is 649mV. |
| doi_str_mv | 10.1109/DDECS.2011.5783112 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5783112</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5783112</ieee_id><sourcerecordid>5783112</sourcerecordid><originalsourceid>FETCH-LOGICAL-i156t-cd0bbafaada56baed1ad5ae8d058396e4dc814014cc8801b0c8fd39d64404e4f3</originalsourceid><addsrcrecordid>eNpFj1FLwzAUhSMiqHN_QF_yBzpz2yRNH0c3pzAV7ATfxm1yK5HajiQO9u9VHHheDh8HPjiMXYOYAYjqdrFY1s0sFwAzVZoCID9hlyBzKatSybfTf1DmnE1j_BA_0boSpbpgT03C5GPyFnuOA_aH6CMfO643vHmZP3KHCXmgREPy48D3Y5_wnfjX4CjwXRgtxcj3GDz-7lfsrMM-0vTYE_Z6t9zU99n6efVQz9eZB6VTZp1oW-wQHSrdIjlAp5CME8oUlSbprAEpQFprjIBWWNO5onJaSiFJdsWE3fx5PRFtd8F_Yjhsj_-Lb6pBUFQ</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Statistical analysis of 6T SRAM data retention voltage under process variation</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Vatajelu, Elena I. ; Figueras, Joan</creator><creatorcontrib>Vatajelu, Elena I. ; Figueras, Joan</creatorcontrib><description>One of the main issues in scaled SRAMs is the increase in static power. A common way to reduce the static power consumption of an SRAM array is to decrease its supply voltage when in memory retention mode. Decreasing the supply voltage however has a strong negative effect on the stability of the SRAM cell. This paper statistically analyzes the behavior of the 6T SRAM cell in data retention mode, under process variability. The failure probabilities under various supply voltages are determined for different technology nodes, and the Data Retention Voltage is determined. For the 45nm PTM SRAM cell under random threshold voltage variation, the Data Retention Voltage is found to be 423mV while for the 16nm PTM SRAM, the DRV is 649mV.</description><identifier>ISBN: 1424497558</identifier><identifier>ISBN: 9781424497553</identifier><identifier>EISBN: 142449754X</identifier><identifier>EISBN: 1424497566</identifier><identifier>EISBN: 9781424497560</identifier><identifier>EISBN: 9781424497546</identifier><identifier>DOI: 10.1109/DDECS.2011.5783112</identifier><language>eng ; jpn</language><publisher>IEEE</publisher><subject>6T SRAM ; Approximation methods ; Data Retention Voltage ; Noise ; Probability ; Process Variability ; Random access memory ; Robustness ; Robustness Analysis ; Threshold voltage ; Transistors</subject><ispartof>14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2011, p.365-370</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5783112$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5783112$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Vatajelu, Elena I.</creatorcontrib><creatorcontrib>Figueras, Joan</creatorcontrib><title>Statistical analysis of 6T SRAM data retention voltage under process variation</title><title>14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems</title><addtitle>DDECS</addtitle><description>One of the main issues in scaled SRAMs is the increase in static power. A common way to reduce the static power consumption of an SRAM array is to decrease its supply voltage when in memory retention mode. Decreasing the supply voltage however has a strong negative effect on the stability of the SRAM cell. This paper statistically analyzes the behavior of the 6T SRAM cell in data retention mode, under process variability. The failure probabilities under various supply voltages are determined for different technology nodes, and the Data Retention Voltage is determined. For the 45nm PTM SRAM cell under random threshold voltage variation, the Data Retention Voltage is found to be 423mV while for the 16nm PTM SRAM, the DRV is 649mV.</description><subject>6T SRAM</subject><subject>Approximation methods</subject><subject>Data Retention Voltage</subject><subject>Noise</subject><subject>Probability</subject><subject>Process Variability</subject><subject>Random access memory</subject><subject>Robustness</subject><subject>Robustness Analysis</subject><subject>Threshold voltage</subject><subject>Transistors</subject><isbn>1424497558</isbn><isbn>9781424497553</isbn><isbn>142449754X</isbn><isbn>1424497566</isbn><isbn>9781424497560</isbn><isbn>9781424497546</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFj1FLwzAUhSMiqHN_QF_yBzpz2yRNH0c3pzAV7ATfxm1yK5HajiQO9u9VHHheDh8HPjiMXYOYAYjqdrFY1s0sFwAzVZoCID9hlyBzKatSybfTf1DmnE1j_BA_0boSpbpgT03C5GPyFnuOA_aH6CMfO643vHmZP3KHCXmgREPy48D3Y5_wnfjX4CjwXRgtxcj3GDz-7lfsrMM-0vTYE_Z6t9zU99n6efVQz9eZB6VTZp1oW-wQHSrdIjlAp5CME8oUlSbprAEpQFprjIBWWNO5onJaSiFJdsWE3fx5PRFtd8F_Yjhsj_-Lb6pBUFQ</recordid><startdate>201104</startdate><enddate>201104</enddate><creator>Vatajelu, Elena I.</creator><creator>Figueras, Joan</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201104</creationdate><title>Statistical analysis of 6T SRAM data retention voltage under process variation</title><author>Vatajelu, Elena I. ; Figueras, Joan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i156t-cd0bbafaada56baed1ad5ae8d058396e4dc814014cc8801b0c8fd39d64404e4f3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng ; jpn</language><creationdate>2011</creationdate><topic>6T SRAM</topic><topic>Approximation methods</topic><topic>Data Retention Voltage</topic><topic>Noise</topic><topic>Probability</topic><topic>Process Variability</topic><topic>Random access memory</topic><topic>Robustness</topic><topic>Robustness Analysis</topic><topic>Threshold voltage</topic><topic>Transistors</topic><toplevel>online_resources</toplevel><creatorcontrib>Vatajelu, Elena I.</creatorcontrib><creatorcontrib>Figueras, Joan</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Xplore</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Vatajelu, Elena I.</au><au>Figueras, Joan</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Statistical analysis of 6T SRAM data retention voltage under process variation</atitle><btitle>14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems</btitle><stitle>DDECS</stitle><date>2011-04</date><risdate>2011</risdate><spage>365</spage><epage>370</epage><pages>365-370</pages><isbn>1424497558</isbn><isbn>9781424497553</isbn><eisbn>142449754X</eisbn><eisbn>1424497566</eisbn><eisbn>9781424497560</eisbn><eisbn>9781424497546</eisbn><abstract>One of the main issues in scaled SRAMs is the increase in static power. A common way to reduce the static power consumption of an SRAM array is to decrease its supply voltage when in memory retention mode. Decreasing the supply voltage however has a strong negative effect on the stability of the SRAM cell. This paper statistically analyzes the behavior of the 6T SRAM cell in data retention mode, under process variability. The failure probabilities under various supply voltages are determined for different technology nodes, and the Data Retention Voltage is determined. For the 45nm PTM SRAM cell under random threshold voltage variation, the Data Retention Voltage is found to be 423mV while for the 16nm PTM SRAM, the DRV is 649mV.</abstract><pub>IEEE</pub><doi>10.1109/DDECS.2011.5783112</doi><tpages>6</tpages></addata></record> |
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| language | eng ; jpn |
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| subjects | 6T SRAM Approximation methods Data Retention Voltage Noise Probability Process Variability Random access memory Robustness Robustness Analysis Threshold voltage Transistors |
| title | Statistical analysis of 6T SRAM data retention voltage under process variation |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-04T16%3A09%3A48IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Statistical%20analysis%20of%206T%20SRAM%20data%20retention%20voltage%20under%20process%20variation&rft.btitle=14th%20IEEE%20International%20Symposium%20on%20Design%20and%20Diagnostics%20of%20Electronic%20Circuits%20and%20Systems&rft.au=Vatajelu,%20Elena%20I.&rft.date=2011-04&rft.spage=365&rft.epage=370&rft.pages=365-370&rft.isbn=1424497558&rft.isbn_list=9781424497553&rft_id=info:doi/10.1109/DDECS.2011.5783112&rft_dat=%3Cieee_6IE%3E5783112%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=142449754X&rft.eisbn_list=1424497566&rft.eisbn_list=9781424497560&rft.eisbn_list=9781424497546&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5783112&rfr_iscdi=true |