A novel low-latency parallel architecture for digital PLL with application to ultra-high speed carrier recovery systems

This paper introduces a new low latency parallel processing digital carrier recovery (CR) architecture suitable for ultra-high speed intradyne coherent optical receivers (e.g. ≥ 100Gb/s). The proposed parallel scheme builds upon a novel digital phase locked loop (DPLL) architecture, which breaks the...

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Bibliographische Detailangaben

Hauptverfasser:	Gianni, P, Carrer, H S, Corral-Briones, G, Hueda, M R
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Bandwidth Jitter Phase locked loops Phase noise Phase shift keying Receivers Signal to noise ratio
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