A novel low-latency parallel architecture for digital PLL with application to ultra-high speed carrier recovery systems

This paper introduces a new low latency parallel processing digital carrier recovery (CR) architecture suitable for ultra-high speed intradyne coherent optical receivers (e.g. ≥ 100Gb/s). The proposed parallel scheme builds upon a novel digital phase locked loop (DPLL) architecture, which breaks the...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Gianni, P, Carrer, H S, Corral-Briones, G, Hueda, M R
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Bandwidth Jitter Phase locked loops Phase noise Phase shift keying Receivers Signal to noise ratio
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page	36
container_issue
container_start_page	31
container_title
container_volume
creator	Gianni, P Carrer, H S Corral-Briones, G Hueda, M R
description	This paper introduces a new low latency parallel processing digital carrier recovery (CR) architecture suitable for ultra-high speed intradyne coherent optical receivers (e.g. ≥ 100Gb/s). The proposed parallel scheme builds upon a novel digital phase locked loop (DPLL) architecture, which breaks the bottleneck of the feedback path. Thus, it is avoided the high latency introduced by the parallel processing implementation in the feedback loop of traditional DPLLs. Numerical results show that the bandwidth and the capture range of the new parallel DPLL are close to those achieved by a serial DPLL. This excellent behavior makes the proposed low latency parallel DPLL architecture an excellent choice for implementing high speed CR systems in both ASIC and FPGA platforms.
doi_str_mv	10.1109/SPL.2011.5782621
format	Conference Proceeding
fullrecord	<record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5782621</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5782621</ieee_id><sourcerecordid>5782621</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-8cee6bfff43813d9899cad5385e4c3bf6240e67e55fefad2d08eadc5235f43f3</originalsourceid><addsrcrecordid>eNpFUM1KAzEYjIig1t4FL3mBrflv9liKWmHBQj14K2nypRtJu0uSWvbtXbDgXIYZmBkYhB4pmVFK6ufNupkxQulMzjVTjF6heyqYEFoL9XX9L-b6Fk1z_iYjlKolI3fovMDH7gcijt25iqbA0Q64N8nEOJom2TYUsOWUAPsuYRf2oZiI102Dz6G02PR9DNaU0B1x6fAplmSqNuxbnHsAh61JKUDCCew4kwach1zgkB_QjTcxw_TCE7R5fflcrqrm4-19uWiqUJNSaQugdt57wTXlrtZ1bY2TXEsQlu-8YoKAmoOUHrxxzBENxlnJuBwjnk_Q019rAIBtn8LBpGF7uYn_ArqsXyc</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A novel low-latency parallel architecture for digital PLL with application to ultra-high speed carrier recovery systems</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Gianni, P ; Carrer, H S ; Corral-Briones, G ; Hueda, M R</creator><creatorcontrib>Gianni, P ; Carrer, H S ; Corral-Briones, G ; Hueda, M R</creatorcontrib><description>This paper introduces a new low latency parallel processing digital carrier recovery (CR) architecture suitable for ultra-high speed intradyne coherent optical receivers (e.g. ≥ 100Gb/s). The proposed parallel scheme builds upon a novel digital phase locked loop (DPLL) architecture, which breaks the bottleneck of the feedback path. Thus, it is avoided the high latency introduced by the parallel processing implementation in the feedback loop of traditional DPLLs. Numerical results show that the bandwidth and the capture range of the new parallel DPLL are close to those achieved by a serial DPLL. This excellent behavior makes the proposed low latency parallel DPLL architecture an excellent choice for implementing high speed CR systems in both ASIC and FPGA platforms.</description><identifier>ISBN: 1424488478</identifier><identifier>ISBN: 9781424488476</identifier><identifier>EISBN: 142448846X</identifier><identifier>EISBN: 1424488486</identifier><identifier>EISBN: 9781424488483</identifier><identifier>EISBN: 9781424488469</identifier><identifier>DOI: 10.1109/SPL.2011.5782621</identifier><language>eng</language><publisher>IEEE</publisher><subject>Bandwidth ; Jitter ; Phase locked loops ; Phase noise ; Phase shift keying ; Receivers ; Signal to noise ratio</subject><ispartof>2011 VII Southern Conference on Programmable Logic (SPL), 2011, p.31-36</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5782621$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,778,782,787,788,2054,27908,54903</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5782621$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Gianni, P</creatorcontrib><creatorcontrib>Carrer, H S</creatorcontrib><creatorcontrib>Corral-Briones, G</creatorcontrib><creatorcontrib>Hueda, M R</creatorcontrib><title>A novel low-latency parallel architecture for digital PLL with application to ultra-high speed carrier recovery systems</title><title>2011 VII Southern Conference on Programmable Logic (SPL)</title><addtitle>SPL</addtitle><description>This paper introduces a new low latency parallel processing digital carrier recovery (CR) architecture suitable for ultra-high speed intradyne coherent optical receivers (e.g. ≥ 100Gb/s). The proposed parallel scheme builds upon a novel digital phase locked loop (DPLL) architecture, which breaks the bottleneck of the feedback path. Thus, it is avoided the high latency introduced by the parallel processing implementation in the feedback loop of traditional DPLLs. Numerical results show that the bandwidth and the capture range of the new parallel DPLL are close to those achieved by a serial DPLL. This excellent behavior makes the proposed low latency parallel DPLL architecture an excellent choice for implementing high speed CR systems in both ASIC and FPGA platforms.</description><subject>Bandwidth</subject><subject>Jitter</subject><subject>Phase locked loops</subject><subject>Phase noise</subject><subject>Phase shift keying</subject><subject>Receivers</subject><subject>Signal to noise ratio</subject><isbn>1424488478</isbn><isbn>9781424488476</isbn><isbn>142448846X</isbn><isbn>1424488486</isbn><isbn>9781424488483</isbn><isbn>9781424488469</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpFUM1KAzEYjIig1t4FL3mBrflv9liKWmHBQj14K2nypRtJu0uSWvbtXbDgXIYZmBkYhB4pmVFK6ufNupkxQulMzjVTjF6heyqYEFoL9XX9L-b6Fk1z_iYjlKolI3fovMDH7gcijt25iqbA0Q64N8nEOJom2TYUsOWUAPsuYRf2oZiI102Dz6G02PR9DNaU0B1x6fAplmSqNuxbnHsAh61JKUDCCew4kwach1zgkB_QjTcxw_TCE7R5fflcrqrm4-19uWiqUJNSaQugdt57wTXlrtZ1bY2TXEsQlu-8YoKAmoOUHrxxzBENxlnJuBwjnk_Q019rAIBtn8LBpGF7uYn_ArqsXyc</recordid><startdate>201104</startdate><enddate>201104</enddate><creator>Gianni, P</creator><creator>Carrer, H S</creator><creator>Corral-Briones, G</creator><creator>Hueda, M R</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201104</creationdate><title>A novel low-latency parallel architecture for digital PLL with application to ultra-high speed carrier recovery systems</title><author>Gianni, P ; Carrer, H S ; Corral-Briones, G ; Hueda, M R</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-8cee6bfff43813d9899cad5385e4c3bf6240e67e55fefad2d08eadc5235f43f3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2011</creationdate><topic>Bandwidth</topic><topic>Jitter</topic><topic>Phase locked loops</topic><topic>Phase noise</topic><topic>Phase shift keying</topic><topic>Receivers</topic><topic>Signal to noise ratio</topic><toplevel>online_resources</toplevel><creatorcontrib>Gianni, P</creatorcontrib><creatorcontrib>Carrer, H S</creatorcontrib><creatorcontrib>Corral-Briones, G</creatorcontrib><creatorcontrib>Hueda, M R</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Gianni, P</au><au>Carrer, H S</au><au>Corral-Briones, G</au><au>Hueda, M R</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A novel low-latency parallel architecture for digital PLL with application to ultra-high speed carrier recovery systems</atitle><btitle>2011 VII Southern Conference on Programmable Logic (SPL)</btitle><stitle>SPL</stitle><date>2011-04</date><risdate>2011</risdate><spage>31</spage><epage>36</epage><pages>31-36</pages><isbn>1424488478</isbn><isbn>9781424488476</isbn><eisbn>142448846X</eisbn><eisbn>1424488486</eisbn><eisbn>9781424488483</eisbn><eisbn>9781424488469</eisbn><abstract>This paper introduces a new low latency parallel processing digital carrier recovery (CR) architecture suitable for ultra-high speed intradyne coherent optical receivers (e.g. ≥ 100Gb/s). The proposed parallel scheme builds upon a novel digital phase locked loop (DPLL) architecture, which breaks the bottleneck of the feedback path. Thus, it is avoided the high latency introduced by the parallel processing implementation in the feedback loop of traditional DPLLs. Numerical results show that the bandwidth and the capture range of the new parallel DPLL are close to those achieved by a serial DPLL. This excellent behavior makes the proposed low latency parallel DPLL architecture an excellent choice for implementing high speed CR systems in both ASIC and FPGA platforms.</abstract><pub>IEEE</pub><doi>10.1109/SPL.2011.5782621</doi><tpages>6</tpages></addata></record>
fulltext	fulltext_linktorsrc
identifier	ISBN: 1424488478
ispartof	2011 VII Southern Conference on Programmable Logic (SPL), 2011, p.31-36
issn
language	eng
recordid	cdi_ieee_primary_5782621
source	IEEE Electronic Library (IEL) Conference Proceedings
subjects	Bandwidth Jitter Phase locked loops Phase noise Phase shift keying Receivers Signal to noise ratio
title	A novel low-latency parallel architecture for digital PLL with application to ultra-high speed carrier recovery systems
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-16T19%3A50%3A50IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20novel%20low-latency%20parallel%20architecture%20for%20digital%20PLL%20with%20application%20to%20ultra-high%20speed%20carrier%20recovery%20systems&rft.btitle=2011%20VII%20Southern%20Conference%20on%20Programmable%20Logic%20(SPL)&rft.au=Gianni,%20P&rft.date=2011-04&rft.spage=31&rft.epage=36&rft.pages=31-36&rft.isbn=1424488478&rft.isbn_list=9781424488476&rft_id=info:doi/10.1109/SPL.2011.5782621&rft_dat=%3Cieee_6IE%3E5782621%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=142448846X&rft.eisbn_list=1424488486&rft.eisbn_list=9781424488483&rft.eisbn_list=9781424488469&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5782621&rfr_iscdi=true