Design of a novel domino XNOR gate for 32 nm-node CMOS technology

A novel domino XNOR gate is designed, using techniques of pn mixed pull-down network and dual-threshold voltage. HSPICE simulation results prove that compared with the standard n-type domino XNOR gate the dynamic power of proposed design can be reduced by 43.9% and the minimum static power is reduce...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Baozeng Guo, Tao Ma, Yubo Zhang
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Dynamic power Inverters Leakage current Logic gates Minimum static power Noise Noise immunity Power demand Threshold voltage Transistors XNOR Gate
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