A novel nanoscale staggered 6T SRAM cell layout to mitigate multiple nodes charge collection effect

As CMOS device size shrinks, the spacing of the sensitive devices in one memory bit is decreased. But the width of the single-event charge track does not shrink, so one particle probably affects several sensitive devices in one memory bit. In this paper, a novel nanoscale 6T SRAM cell layout is prop...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Chengmin Xie, Zhongfang Wang, Fuxin Yan, Longsheng Wu, Youbao Liu
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	CMOS integrated circuits critical charge Equations Layout multiple nodes charge collection nanoscale Nanoscale devices Neutrons Random access memory single-event upset SRAM cell Transistors
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