A parallel unification machine
A parallel unification machine (PUM) that speeds up the unification algorithm is proposed. The PUM partitions unification into a match step and a consistency-check step, conducts these two steps concurrently, and takes advantage of the match parallelism. The machine architecture, algorithms, data fo...
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Veröffentlicht in: | IEEE MICRO 1990-08, Vol.10 (4), p.21-33 |
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creator | Sibai, F.N. Watson, K.L. Lu, M. |
description | A parallel unification machine (PUM) that speeds up the unification algorithm is proposed. The PUM partitions unification into a match step and a consistency-check step, conducts these two steps concurrently, and takes advantage of the match parallelism. The machine architecture, algorithms, data formats, and processor organization are described. The machine has been simulated at the register-transfer level with the ISPS computer description language. The simulated performance is compared with that of two serial unification coprocessors. Significant speedup is observed.< > |
doi_str_mv | 10.1109/40.57728 |
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The PUM partitions unification into a match step and a consistency-check step, conducts these two steps concurrently, and takes advantage of the match parallelism. The machine architecture, algorithms, data formats, and processor organization are described. The machine has been simulated at the register-transfer level with the ISPS computer description language. The simulated performance is compared with that of two serial unification coprocessors. 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The PUM partitions unification into a match step and a consistency-check step, conducts these two steps concurrently, and takes advantage of the match parallelism. The machine architecture, algorithms, data formats, and processor organization are described. The machine has been simulated at the register-transfer level with the ISPS computer description language. The simulated performance is compared with that of two serial unification coprocessors. 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The PUM partitions unification into a match step and a consistency-check step, conducts these two steps concurrently, and takes advantage of the match parallelism. The machine architecture, algorithms, data formats, and processor organization are described. The machine has been simulated at the register-transfer level with the ISPS computer description language. The simulated performance is compared with that of two serial unification coprocessors. Significant speedup is observed.< ></abstract><pub>IEEE</pub><doi>10.1109/40.57728</doi><tpages>13</tpages></addata></record> |
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subjects | Application software Artificial intelligence Expert systems Image databases Logic programming Magnetic heads Natural languages Runtime Spatial databases Speech |
title | A parallel unification machine |
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