CAS-FEST 2010: Mitigating Variability in Near-Threshold Computing

Near threshold computing has recently gained significant interest due to its potential to address the prohibitive increase of power consumption in a wide spectrum of modern VLSI circuits. This tutorial paper starts by reviewing the benefits and challenges of near threshold computing. We focus on the...

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Veröffentlicht in:	IEEE journal on emerging and selected topics in circuits and systems 2011-03, Vol.1 (1), p.42-49
Hauptverfasser:	Mingoo Seok, Chen, Gregory, Hanson, Scott, Wieckowski, Michael, Blaauw, David, Sylvester, Dennis
Format:	Artikel
Sprache:	eng
Schlagworte:	Clocks Delay Logic gates Low voltage near threshold computing Performance evaluation Random access memory Synchronization Threshold voltage variability
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creator	Mingoo Seok Chen, Gregory Hanson, Scott Wieckowski, Michael Blaauw, David Sylvester, Dennis
description	Near threshold computing has recently gained significant interest due to its potential to address the prohibitive increase of power consumption in a wide spectrum of modern VLSI circuits. This tutorial paper starts by reviewing the benefits and challenges of near threshold computing. We focus on the challenge of variability and discuss circuit and architecture solutions tailored to three different circuit fabrics: logic, memory, and clock distribution. Soft-edge clocking, body-biasing, mismatch-tolerant memories, asynchronous operation and low-skew clock networks are presented to mitigate variability in the near threshold V DD regime.
doi_str_mv	10.1109/JETCAS.2011.2135550
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subjects	Clocks Delay Logic gates Low voltage near threshold computing Performance evaluation Random access memory Synchronization Threshold voltage variability
title	CAS-FEST 2010: Mitigating Variability in Near-Threshold Computing
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