High performance 3D interconnects based on electrochemical etch and liquid metal fill
Besides the usually known TSV technologies to etch and fill Si interconnects there is a powerful photo-assisted electrochemical etch technology for fine pitch TSV, which goes hand in hand with a liquid fill metallization. Both together allow the generation of high density wiring on and through thick...
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creator | Hedler, H Scheiter, T Schieber, M Klumpp, A Ramm, P |
description | Besides the usually known TSV technologies to etch and fill Si interconnects there is a powerful photo-assisted electrochemical etch technology for fine pitch TSV, which goes hand in hand with a liquid fill metallization. Both together allow the generation of high density wiring on and through thick self-carrying interposers, where other technologies fail. Together with any etching technology the liquid fill technology allows an extremely simple process flow to realize conductor lines inside buried channels. Taking the right material combinations there is very low stress inside the substrate, which allows a high design freedom for larger via or systematic aligned via. Using the fill technology for stacked dies an extremely simple and compact 3D wiring is possible. It is less complex than conventional ones since it does not need any seed layer or additional balls between chips. The fill technology has the potential of complete wiring of multichip systems. |
doi_str_mv | 10.1109/3DIC.2010.5751449 |
format | Conference Proceeding |
fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5751449</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5751449</ieee_id><sourcerecordid>5751449</sourcerecordid><originalsourceid>FETCH-ieee_primary_57514493</originalsourceid><addsrcrecordid>eNp9jrEOgjAURWuMiUb5AOPyfkBtgVKZUaO7zqSWh9SUgm0d_HsZXFy8y805d7mELBndMEbzbbI_F5uYDsgFZ2maj0iUix1LuRCUx5yOfzgTUxJ5_6BDslgIns7I9aTvDfTo6s610iqEZA_aBnSqsxZV8HCTHivoLKAZ2HWqwVYraQCDakDaCox-vnQFLYbB1tqYBZnU0niMvj0nq-PhUpzWGhHL3ulWunf5PZ38Xz8VKUOs</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>High performance 3D interconnects based on electrochemical etch and liquid metal fill</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Hedler, H ; Scheiter, T ; Schieber, M ; Klumpp, A ; Ramm, P</creator><creatorcontrib>Hedler, H ; Scheiter, T ; Schieber, M ; Klumpp, A ; Ramm, P</creatorcontrib><description>Besides the usually known TSV technologies to etch and fill Si interconnects there is a powerful photo-assisted electrochemical etch technology for fine pitch TSV, which goes hand in hand with a liquid fill metallization. Both together allow the generation of high density wiring on and through thick self-carrying interposers, where other technologies fail. Together with any etching technology the liquid fill technology allows an extremely simple process flow to realize conductor lines inside buried channels. Taking the right material combinations there is very low stress inside the substrate, which allows a high design freedom for larger via or systematic aligned via. Using the fill technology for stacked dies an extremely simple and compact 3D wiring is possible. It is less complex than conventional ones since it does not need any seed layer or additional balls between chips. The fill technology has the potential of complete wiring of multichip systems.</description><identifier>ISBN: 9781457705267</identifier><identifier>ISBN: 1457705265</identifier><identifier>EISBN: 9781457705250</identifier><identifier>EISBN: 9781457705274</identifier><identifier>EISBN: 1457705273</identifier><identifier>EISBN: 1457705257</identifier><identifier>DOI: 10.1109/3DIC.2010.5751449</identifier><language>eng</language><publisher>IEEE</publisher><subject>Filling ; Silicon ; Stacking ; Substrates ; Through-silicon vias ; Wiring</subject><ispartof>2010 IEEE International 3D Systems Integration Conference (3DIC), 2010, p.1-7</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5751449$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5751449$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Hedler, H</creatorcontrib><creatorcontrib>Scheiter, T</creatorcontrib><creatorcontrib>Schieber, M</creatorcontrib><creatorcontrib>Klumpp, A</creatorcontrib><creatorcontrib>Ramm, P</creatorcontrib><title>High performance 3D interconnects based on electrochemical etch and liquid metal fill</title><title>2010 IEEE International 3D Systems Integration Conference (3DIC)</title><addtitle>3DIC</addtitle><description>Besides the usually known TSV technologies to etch and fill Si interconnects there is a powerful photo-assisted electrochemical etch technology for fine pitch TSV, which goes hand in hand with a liquid fill metallization. Both together allow the generation of high density wiring on and through thick self-carrying interposers, where other technologies fail. Together with any etching technology the liquid fill technology allows an extremely simple process flow to realize conductor lines inside buried channels. Taking the right material combinations there is very low stress inside the substrate, which allows a high design freedom for larger via or systematic aligned via. Using the fill technology for stacked dies an extremely simple and compact 3D wiring is possible. It is less complex than conventional ones since it does not need any seed layer or additional balls between chips. The fill technology has the potential of complete wiring of multichip systems.</description><subject>Filling</subject><subject>Silicon</subject><subject>Stacking</subject><subject>Substrates</subject><subject>Through-silicon vias</subject><subject>Wiring</subject><isbn>9781457705267</isbn><isbn>1457705265</isbn><isbn>9781457705250</isbn><isbn>9781457705274</isbn><isbn>1457705273</isbn><isbn>1457705257</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9jrEOgjAURWuMiUb5AOPyfkBtgVKZUaO7zqSWh9SUgm0d_HsZXFy8y805d7mELBndMEbzbbI_F5uYDsgFZ2maj0iUix1LuRCUx5yOfzgTUxJ5_6BDslgIns7I9aTvDfTo6s610iqEZA_aBnSqsxZV8HCTHivoLKAZ2HWqwVYraQCDakDaCox-vnQFLYbB1tqYBZnU0niMvj0nq-PhUpzWGhHL3ulWunf5PZ38Xz8VKUOs</recordid><startdate>201011</startdate><enddate>201011</enddate><creator>Hedler, H</creator><creator>Scheiter, T</creator><creator>Schieber, M</creator><creator>Klumpp, A</creator><creator>Ramm, P</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201011</creationdate><title>High performance 3D interconnects based on electrochemical etch and liquid metal fill</title><author>Hedler, H ; Scheiter, T ; Schieber, M ; Klumpp, A ; Ramm, P</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_57514493</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Filling</topic><topic>Silicon</topic><topic>Stacking</topic><topic>Substrates</topic><topic>Through-silicon vias</topic><topic>Wiring</topic><toplevel>online_resources</toplevel><creatorcontrib>Hedler, H</creatorcontrib><creatorcontrib>Scheiter, T</creatorcontrib><creatorcontrib>Schieber, M</creatorcontrib><creatorcontrib>Klumpp, A</creatorcontrib><creatorcontrib>Ramm, P</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hedler, H</au><au>Scheiter, T</au><au>Schieber, M</au><au>Klumpp, A</au><au>Ramm, P</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>High performance 3D interconnects based on electrochemical etch and liquid metal fill</atitle><btitle>2010 IEEE International 3D Systems Integration Conference (3DIC)</btitle><stitle>3DIC</stitle><date>2010-11</date><risdate>2010</risdate><spage>1</spage><epage>7</epage><pages>1-7</pages><isbn>9781457705267</isbn><isbn>1457705265</isbn><eisbn>9781457705250</eisbn><eisbn>9781457705274</eisbn><eisbn>1457705273</eisbn><eisbn>1457705257</eisbn><abstract>Besides the usually known TSV technologies to etch and fill Si interconnects there is a powerful photo-assisted electrochemical etch technology for fine pitch TSV, which goes hand in hand with a liquid fill metallization. Both together allow the generation of high density wiring on and through thick self-carrying interposers, where other technologies fail. Together with any etching technology the liquid fill technology allows an extremely simple process flow to realize conductor lines inside buried channels. Taking the right material combinations there is very low stress inside the substrate, which allows a high design freedom for larger via or systematic aligned via. Using the fill technology for stacked dies an extremely simple and compact 3D wiring is possible. It is less complex than conventional ones since it does not need any seed layer or additional balls between chips. The fill technology has the potential of complete wiring of multichip systems.</abstract><pub>IEEE</pub><doi>10.1109/3DIC.2010.5751449</doi></addata></record> |
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subjects | Filling Silicon Stacking Substrates Through-silicon vias Wiring |
title | High performance 3D interconnects based on electrochemical etch and liquid metal fill |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-03T06%3A24%3A36IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=High%20performance%203D%20interconnects%20based%20on%20electrochemical%20etch%20and%20liquid%20metal%20fill&rft.btitle=2010%20IEEE%20International%203D%20Systems%20Integration%20Conference%20(3DIC)&rft.au=Hedler,%20H&rft.date=2010-11&rft.spage=1&rft.epage=7&rft.pages=1-7&rft.isbn=9781457705267&rft.isbn_list=1457705265&rft_id=info:doi/10.1109/3DIC.2010.5751449&rft_dat=%3Cieee_6IE%3E5751449%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781457705250&rft.eisbn_list=9781457705274&rft.eisbn_list=1457705273&rft.eisbn_list=1457705257&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5751449&rfr_iscdi=true |