A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology
Recently, the demand for 3b/cell NAND flash has been increasing due to a strong market shift from 2b/cell to 3b/cell in NAND flash applications, such as USB disk drives, memory cards, MP3 players and digital still cameras that require cost effective flash memory. To further expand the 3b/cell market...
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| creator | Ki-Tae Park Ohsuk Kwon Sangyong Yoon Myung-Hoon Choi In-Mo Kim Bo-Geun Kim Min-Seok Kim Yoon-Hee Choi Seung-Hwan Shin Youngson Song Joo-Yong Park Jae-Eun Lee Chang-Gyu Eun Ho-Chul Lee Hyeong-Jun Kim Jun-Hee Lee Jong-Young Kim Tae-Min Kweon Hyun-Jun Yoon Taehyun Kim Dong-Kyo Shim Jongsun Sel Ji-Yeon Shin Pansuk Kwak Jin-Man Han Keon-Soo Kim Sungsoo Lee Young-Ho Lim Tae-Sung Jung |
| description | Recently, the demand for 3b/cell NAND flash has been increasing due to a strong market shift from 2b/cell to 3b/cell in NAND flash applications, such as USB disk drives, memory cards, MP3 players and digital still cameras that require cost effective flash memory. To further expand the 3b/cell market, high write and read performances are essential. Moreover, the device reliability requirements for these applications is a challenge due to continuing NAND scaling to sub-30nm pitches that increases cell-to-cell interference and disturbance. We present a high reliability 64Gb 3b/cell NAND flash with 7MB/s write rate and 200Mb/s asynchronous DDR interface in a 20m-node technology that helps to meet the expanding market demand and application requirement. |
| doi_str_mv | 10.1109/ISSCC.2011.5746287 |
| format | Conference Proceeding |
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We present a high reliability 64Gb 3b/cell NAND flash with 7MB/s write rate and 200Mb/s asynchronous DDR interface in a 20m-node technology that helps to meet the expanding market demand and application requirement.</description><subject>Computer architecture</subject><subject>Decoding</subject><subject>Flash memory</subject><subject>Latches</subject><subject>Microprocessors</subject><subject>Reliability</subject><subject>Tunneling</subject><issn>0193-6530</issn><issn>2376-8606</issn><isbn>9781612843032</isbn><isbn>1612843034</isbn><isbn>1612843026</isbn><isbn>9781612843018</isbn><isbn>1612843018</isbn><isbn>9781612843025</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2011</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1kM1OAjEUhetf4ojzArrpCxR6e9s77RIHRBLERNiTlunImPkxDBveHox4Nmdxki85H2NPIIcA0o3mq1WeD5UEGJpMk7LZFXsAAmU1SkXXLFGYkbAk6YalLrP_G6pblkhwKMigvGdp33_Lc4icsSZh0zHP3l9GPSc9CxxFqA6jbaxrPpl88uV4OeFl7fsdb2LT7Y-8armSbSParoj8ELe7tqu7r-Mjuyt93cf00gO2fp2u8zex-JjN8_FCVE4eBHrnQ4naB_Lgo7YEFtDarS5cJh1aA4VXoIrfh6gpmOitKQ2EswJlCAfs-Q9bxRg3P_uq8fvj5iIETwFMS1s</recordid><startdate>201102</startdate><enddate>201102</enddate><creator>Ki-Tae Park</creator><creator>Ohsuk Kwon</creator><creator>Sangyong Yoon</creator><creator>Myung-Hoon Choi</creator><creator>In-Mo Kim</creator><creator>Bo-Geun Kim</creator><creator>Min-Seok Kim</creator><creator>Yoon-Hee Choi</creator><creator>Seung-Hwan Shin</creator><creator>Youngson Song</creator><creator>Joo-Yong Park</creator><creator>Jae-Eun Lee</creator><creator>Chang-Gyu Eun</creator><creator>Ho-Chul Lee</creator><creator>Hyeong-Jun Kim</creator><creator>Jun-Hee Lee</creator><creator>Jong-Young Kim</creator><creator>Tae-Min Kweon</creator><creator>Hyun-Jun Yoon</creator><creator>Taehyun Kim</creator><creator>Dong-Kyo Shim</creator><creator>Jongsun Sel</creator><creator>Ji-Yeon Shin</creator><creator>Pansuk Kwak</creator><creator>Jin-Man Han</creator><creator>Keon-Soo Kim</creator><creator>Sungsoo Lee</creator><creator>Young-Ho Lim</creator><creator>Tae-Sung Jung</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201102</creationdate><title>A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology</title><author>Ki-Tae Park ; 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To further expand the 3b/cell market, high write and read performances are essential. Moreover, the device reliability requirements for these applications is a challenge due to continuing NAND scaling to sub-30nm pitches that increases cell-to-cell interference and disturbance. We present a high reliability 64Gb 3b/cell NAND flash with 7MB/s write rate and 200Mb/s asynchronous DDR interface in a 20m-node technology that helps to meet the expanding market demand and application requirement.</abstract><pub>IEEE</pub><doi>10.1109/ISSCC.2011.5746287</doi><tpages>2</tpages></addata></record> |
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| identifier | ISSN: 0193-6530 |
| ispartof | 2011 IEEE International Solid-State Circuits Conference, 2011, p.212-213 |
| issn | 0193-6530 2376-8606 |
| language | eng |
| recordid | cdi_ieee_primary_5746287 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Computer architecture Decoding Flash memory Latches Microprocessors Reliability Tunneling |
| title | A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology |
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