Low-power fast static random access memory cell

In this paper, we propose a new circuit-level technique to reduce the delay and power in SRAM cell during write operation. The proposed low-power fast (LPF) static random access memory (SRAM) cell contains two extra tail transistors in the respective inverter to avoid the charging or discharging of...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Prabhu, C M R, Singh, Ajay Kumar
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Computer architecture Delay Microprocessors Power demand Random access memory Stability analysis Static noise margin Static random access memory cell Tail transistors Transistors Write power Write/Read delay
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