Low-power fast static random access memory cell

In this paper, we propose a new circuit-level technique to reduce the delay and power in SRAM cell during write operation. The proposed low-power fast (LPF) static random access memory (SRAM) cell contains two extra tail transistors in the respective inverter to avoid the charging or discharging of...

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Hauptverfasser:	Prabhu, C M R, Singh, Ajay Kumar
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Computer architecture Delay Microprocessors Power demand Random access memory Stability analysis Static noise margin Static random access memory cell Tail transistors Transistors Write power Write/Read delay
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creator	Prabhu, C M R Singh, Ajay Kumar
description	In this paper, we propose a new circuit-level technique to reduce the delay and power in SRAM cell during write operation. The proposed low-power fast (LPF) static random access memory (SRAM) cell contains two extra tail transistors in the respective inverter to avoid the charging or discharging of the bit-line. The simulated result shows that the write power saving is at least 86.95% in 0.12μm technology compared to the conventional cell. The access delay is also found to be lower than the conventional SRAM cell during write operation. The static noise margin (SNM) is maintained after carefully sizing the tail transistors.
doi_str_mv	10.1109/ICCAIE.2010.5735036
format	Conference Proceeding
fullrecord	<record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5735036</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5735036</ieee_id><sourcerecordid>5735036</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-c57126900dd821d5a00b550d435ee0bbc22f48ef3a2fb33c43b369c2a44162513</originalsourceid><addsrcrecordid>eNo1j81qwzAQhFVKIW3qJ8hFL-BkpdXa1jGYtDUYesk96GcNLnYcLEPI2zfQdC7DN4cPRoiNgq1SYHdNXe-bw1bDfaASCbB4EpktK2W0MRYI4Vm8_YOhlchS-oF7SJelqV7Frp2u-WW68iw7lxaZFrf0Qc7uHKdRuhA4JTnyOM03GXgY3sVL54bE2aPX4vhxONZfefv92dT7Nu8tLHmgUunCAsRYaRXJAXgiiAaJGbwPWnem4g6d7jxiMOixsEE7Y1ShSeFabP60PTOfLnM_uvl2elzEXxyJQ5M</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>Low-power fast static random access memory cell</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Prabhu, C M R ; Singh, Ajay Kumar</creator><creatorcontrib>Prabhu, C M R ; Singh, Ajay Kumar</creatorcontrib><description>In this paper, we propose a new circuit-level technique to reduce the delay and power in SRAM cell during write operation. The proposed low-power fast (LPF) static random access memory (SRAM) cell contains two extra tail transistors in the respective inverter to avoid the charging or discharging of the bit-line. The simulated result shows that the write power saving is at least 86.95% in 0.12μm technology compared to the conventional cell. The access delay is also found to be lower than the conventional SRAM cell during write operation. The static noise margin (SNM) is maintained after carefully sizing the tail transistors.</description><identifier>ISBN: 1424490545</identifier><identifier>ISBN: 9781424490547</identifier><identifier>EISBN: 9781424490530</identifier><identifier>EISBN: 1424490537</identifier><identifier>EISBN: 1424490553</identifier><identifier>EISBN: 9781424490554</identifier><identifier>DOI: 10.1109/ICCAIE.2010.5735036</identifier><language>eng</language><publisher>IEEE</publisher><subject>Computer architecture ; Delay ; Microprocessors ; Power demand ; Random access memory ; Stability analysis ; Static noise margin ; Static random access memory cell ; Tail transistors ; Transistors ; Write power ; Write/Read delay</subject><ispartof>2010 International Conference on Computer Applications and Industrial Electronics, 2010, p.5-8</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5735036$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2051,27904,54899</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5735036$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Prabhu, C M R</creatorcontrib><creatorcontrib>Singh, Ajay Kumar</creatorcontrib><title>Low-power fast static random access memory cell</title><title>2010 International Conference on Computer Applications and Industrial Electronics</title><addtitle>ICCAIE</addtitle><description>In this paper, we propose a new circuit-level technique to reduce the delay and power in SRAM cell during write operation. The proposed low-power fast (LPF) static random access memory (SRAM) cell contains two extra tail transistors in the respective inverter to avoid the charging or discharging of the bit-line. The simulated result shows that the write power saving is at least 86.95% in 0.12μm technology compared to the conventional cell. The access delay is also found to be lower than the conventional SRAM cell during write operation. The static noise margin (SNM) is maintained after carefully sizing the tail transistors.</description><subject>Computer architecture</subject><subject>Delay</subject><subject>Microprocessors</subject><subject>Power demand</subject><subject>Random access memory</subject><subject>Stability analysis</subject><subject>Static noise margin</subject><subject>Static random access memory cell</subject><subject>Tail transistors</subject><subject>Transistors</subject><subject>Write power</subject><subject>Write/Read delay</subject><isbn>1424490545</isbn><isbn>9781424490547</isbn><isbn>9781424490530</isbn><isbn>1424490537</isbn><isbn>1424490553</isbn><isbn>9781424490554</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1j81qwzAQhFVKIW3qJ8hFL-BkpdXa1jGYtDUYesk96GcNLnYcLEPI2zfQdC7DN4cPRoiNgq1SYHdNXe-bw1bDfaASCbB4EpktK2W0MRYI4Vm8_YOhlchS-oF7SJelqV7Frp2u-WW68iw7lxaZFrf0Qc7uHKdRuhA4JTnyOM03GXgY3sVL54bE2aPX4vhxONZfefv92dT7Nu8tLHmgUunCAsRYaRXJAXgiiAaJGbwPWnem4g6d7jxiMOixsEE7Y1ShSeFabP60PTOfLnM_uvl2elzEXxyJQ5M</recordid><startdate>201012</startdate><enddate>201012</enddate><creator>Prabhu, C M R</creator><creator>Singh, Ajay Kumar</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201012</creationdate><title>Low-power fast static random access memory cell</title><author>Prabhu, C M R ; Singh, Ajay Kumar</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-c57126900dd821d5a00b550d435ee0bbc22f48ef3a2fb33c43b369c2a44162513</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Computer architecture</topic><topic>Delay</topic><topic>Microprocessors</topic><topic>Power demand</topic><topic>Random access memory</topic><topic>Stability analysis</topic><topic>Static noise margin</topic><topic>Static random access memory cell</topic><topic>Tail transistors</topic><topic>Transistors</topic><topic>Write power</topic><topic>Write/Read delay</topic><toplevel>online_resources</toplevel><creatorcontrib>Prabhu, C M R</creatorcontrib><creatorcontrib>Singh, Ajay Kumar</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Prabhu, C M R</au><au>Singh, Ajay Kumar</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Low-power fast static random access memory cell</atitle><btitle>2010 International Conference on Computer Applications and Industrial Electronics</btitle><stitle>ICCAIE</stitle><date>2010-12</date><risdate>2010</risdate><spage>5</spage><epage>8</epage><pages>5-8</pages><isbn>1424490545</isbn><isbn>9781424490547</isbn><eisbn>9781424490530</eisbn><eisbn>1424490537</eisbn><eisbn>1424490553</eisbn><eisbn>9781424490554</eisbn><abstract>In this paper, we propose a new circuit-level technique to reduce the delay and power in SRAM cell during write operation. The proposed low-power fast (LPF) static random access memory (SRAM) cell contains two extra tail transistors in the respective inverter to avoid the charging or discharging of the bit-line. The simulated result shows that the write power saving is at least 86.95% in 0.12μm technology compared to the conventional cell. The access delay is also found to be lower than the conventional SRAM cell during write operation. The static noise margin (SNM) is maintained after carefully sizing the tail transistors.</abstract><pub>IEEE</pub><doi>10.1109/ICCAIE.2010.5735036</doi><tpages>4</tpages></addata></record>
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identifier	ISBN: 1424490545
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source	IEEE Electronic Library (IEL) Conference Proceedings
subjects	Computer architecture Delay Microprocessors Power demand Random access memory Stability analysis Static noise margin Static random access memory cell Tail transistors Transistors Write power Write/Read delay
title	Low-power fast static random access memory cell
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-22T02%3A20%3A14IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Low-power%20fast%20static%20random%20access%20memory%20cell&rft.btitle=2010%20International%20Conference%20on%20Computer%20Applications%20and%20Industrial%20Electronics&rft.au=Prabhu,%20C%20M%20R&rft.date=2010-12&rft.spage=5&rft.epage=8&rft.pages=5-8&rft.isbn=1424490545&rft.isbn_list=9781424490547&rft_id=info:doi/10.1109/ICCAIE.2010.5735036&rft_dat=%3Cieee_6IE%3E5735036%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424490530&rft.eisbn_list=1424490537&rft.eisbn_list=1424490553&rft.eisbn_list=9781424490554&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5735036&rfr_iscdi=true