A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications
A LDPC decoder chip supporting four code rates of IEEE 802.15.3c applications is presented. The row-based layered scheduling with normalized min-sum algorithm is proposed to reduce the iteration number while maintaining similar performance. In addition, the reconfigurable 8/16/32-input sorter is des...
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| creator | Shiang-Yu Hung Shao-Wei Yen Chih-Lung Chen Hsie-Chia Chang Shyh-Jye Jou Chen-Yi Lee |
| description | A LDPC decoder chip supporting four code rates of IEEE 802.15.3c applications is presented. The row-based layered scheduling with normalized min-sum algorithm is proposed to reduce the iteration number while maintaining similar performance. In addition, the reconfigurable 8/16/32-input sorter is designed to deal with four LDPC codes. In order to alleviate routing complexity, both of the reallocation of sorter inputs and pre-coding routing network are proposed to reduce the input numbers of multiplexers by 64%. Fabricated in 65-nm 1P10M CMOS process, this test chip can achieve maximum 5.79 Gbps throughput for the highest code rate code while the hardware efficiency and energy efficiency are 3.7 Gbps/mm 2 and 62.4pJ/bit, respectively. |
| doi_str_mv | 10.1109/ASSCC.2010.5716617 |
| format | Conference Proceeding |
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The row-based layered scheduling with normalized min-sum algorithm is proposed to reduce the iteration number while maintaining similar performance. In addition, the reconfigurable 8/16/32-input sorter is designed to deal with four LDPC codes. In order to alleviate routing complexity, both of the reallocation of sorter inputs and pre-coding routing network are proposed to reduce the input numbers of multiplexers by 64%. Fabricated in 65-nm 1P10M CMOS process, this test chip can achieve maximum 5.79 Gbps throughput for the highest code rate code while the hardware efficiency and energy efficiency are 3.7 Gbps/mm 2 and 62.4pJ/bit, respectively.</abstract><pub>IEEE</pub><doi>10.1109/ASSCC.2010.5716617</doi><tpages>4</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Decoding Hardware Iterative decoding Multiplexing Routing Scheduling |
| title | A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications |
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