A novel BE-SONOS NAND Flash using non-cut trapping layer with superb reliability

This work presents superb chip-level reliability of a BE-SONOS charge trapping NAND fabricated in both 75nm and 38nm half-pitches. Without any error correction (ECC) >;100K P/E cycling endurance for SLC and >;3K endurance for MLC are obtained using a novel non-cut SiN trapping layer. Key proce...

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Hauptverfasser:	Chih-Chang Hsieh, Hang-Ting Lue, Kuo-Pin Chang, Yi-Hsuan Hsiao, Tzu-Hsuan Hsu, Chih-Ping Chen, Yin-Jen Chen, Kuan-Fu Chen, Lo, Chester, Tzung-Ting Han, Ming-Shiang Chen, Wen-Pin Lu, Szu-Yu Wang, Jeng-Hwa Liao, Shih-Ping Hong, Fang-Hao Hsu, Tahone Yang, Kuang-Chao Chen, Kuang-Yeu Hsieh, Chih-Yuan Lu
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Charge carrier processes Degradation Doping Logic gates Reliability Silicon compounds Stress
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