A novel BE-SONOS NAND Flash using non-cut trapping layer with superb reliability
This work presents superb chip-level reliability of a BE-SONOS charge trapping NAND fabricated in both 75nm and 38nm half-pitches. Without any error correction (ECC) >;100K P/E cycling endurance for SLC and >;3K endurance for MLC are obtained using a novel non-cut SiN trapping layer. Key proce...
Gespeichert in:
| Hauptverfasser: | , , , , , , , , , , , , , , , , , , , |
|---|---|
| Format: | Tagungsbericht |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 5.5.4 |
|---|---|
| container_issue | |
| container_start_page | 5.5.1 |
| container_title | |
| container_volume | |
| creator | Chih-Chang Hsieh Hang-Ting Lue Kuo-Pin Chang Yi-Hsuan Hsiao Tzu-Hsuan Hsu Chih-Ping Chen Yin-Jen Chen Kuan-Fu Chen Lo, Chester Tzung-Ting Han Ming-Shiang Chen Wen-Pin Lu Szu-Yu Wang Jeng-Hwa Liao Shih-Ping Hong Fang-Hao Hsu Tahone Yang Kuang-Chao Chen Kuang-Yeu Hsieh Chih-Yuan Lu |
| description | This work presents superb chip-level reliability of a BE-SONOS charge trapping NAND fabricated in both 75nm and 38nm half-pitches. Without any error correction (ECC) >;100K P/E cycling endurance for SLC and >;3K endurance for MLC are obtained using a novel non-cut SiN trapping layer. Key process integration strategies are discussed, including barrier and trapping layer engineering, p-well and junction doping optimization, gate-etching profile, and SSL/GSL processing. In addition to the overall good performance in programming/erasing and reliability, the non-cut SiN also demonstrated charge retention without any lateral spread - contrary to common misperception of charge migration in SiN. We believe this is the first time the reliability and performance of a charge trapping NAND chip are demonstrated to match or surpass those for FG NAND. |
| doi_str_mv | 10.1109/IEDM.2010.5703303 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_5703303</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>5703303</ieee_id><sourcerecordid>5703303</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-80c71d7688ab3e4f197b46e21a3c03dc3daef3f6cd194daedc2e6283da5709c43</originalsourceid><addsrcrecordid>eNotkElOwzAYhc1QiVB6AMTGF3DxbzselqEDVCoNUrtgVzmOQ41CiZK0qLfHiK7e8Elv8RC6BzoGoOZxMZu-jhmNMVWUc8ov0MgoDYIJoQQYeYkSBqkkFNT71ZlFGJlOr1FCQXICBvQAJRqIFIxpcYNuu-6TUqZSkyboLcP776Ov8dOMrPNVvsarbDXF89p2O3zowv4j8j1xhx73rW2av6K2J9_in9DvcHdofFvg1tfBFqEO_ekODSpbd3501iHazGebyQtZ5s-LSbYkwdCeaOoUlEpqbQvuRQVGFUJ6BpY7ykvHS-srXklXghHRl455yXSs4xXGCT5ED_-zwXu_bdrwZdvT9vwT_wX481Tz</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A novel BE-SONOS NAND Flash using non-cut trapping layer with superb reliability</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Chih-Chang Hsieh ; Hang-Ting Lue ; Kuo-Pin Chang ; Yi-Hsuan Hsiao ; Tzu-Hsuan Hsu ; Chih-Ping Chen ; Yin-Jen Chen ; Kuan-Fu Chen ; Lo, Chester ; Tzung-Ting Han ; Ming-Shiang Chen ; Wen-Pin Lu ; Szu-Yu Wang ; Jeng-Hwa Liao ; Shih-Ping Hong ; Fang-Hao Hsu ; Tahone Yang ; Kuang-Chao Chen ; Kuang-Yeu Hsieh ; Chih-Yuan Lu</creator><creatorcontrib>Chih-Chang Hsieh ; Hang-Ting Lue ; Kuo-Pin Chang ; Yi-Hsuan Hsiao ; Tzu-Hsuan Hsu ; Chih-Ping Chen ; Yin-Jen Chen ; Kuan-Fu Chen ; Lo, Chester ; Tzung-Ting Han ; Ming-Shiang Chen ; Wen-Pin Lu ; Szu-Yu Wang ; Jeng-Hwa Liao ; Shih-Ping Hong ; Fang-Hao Hsu ; Tahone Yang ; Kuang-Chao Chen ; Kuang-Yeu Hsieh ; Chih-Yuan Lu</creatorcontrib><description>This work presents superb chip-level reliability of a BE-SONOS charge trapping NAND fabricated in both 75nm and 38nm half-pitches. Without any error correction (ECC) >;100K P/E cycling endurance for SLC and >;3K endurance for MLC are obtained using a novel non-cut SiN trapping layer. Key process integration strategies are discussed, including barrier and trapping layer engineering, p-well and junction doping optimization, gate-etching profile, and SSL/GSL processing. In addition to the overall good performance in programming/erasing and reliability, the non-cut SiN also demonstrated charge retention without any lateral spread - contrary to common misperception of charge migration in SiN. We believe this is the first time the reliability and performance of a charge trapping NAND chip are demonstrated to match or surpass those for FG NAND.</description><identifier>ISSN: 0163-1918</identifier><identifier>ISBN: 9781442474185</identifier><identifier>ISBN: 1442474181</identifier><identifier>EISSN: 2156-017X</identifier><identifier>EISBN: 9781424474196</identifier><identifier>EISBN: 1424474191</identifier><identifier>EISBN: 1424474205</identifier><identifier>EISBN: 9781424474202</identifier><identifier>DOI: 10.1109/IEDM.2010.5703303</identifier><identifier>LCCN: 81-642284</identifier><language>eng</language><publisher>IEEE</publisher><subject>Charge carrier processes ; Degradation ; Doping ; Logic gates ; Reliability ; Silicon compounds ; Stress</subject><ispartof>2010 International Electron Devices Meeting, 2010, p.5.5.1-5.5.4</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5703303$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,27916,54911</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5703303$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Chih-Chang Hsieh</creatorcontrib><creatorcontrib>Hang-Ting Lue</creatorcontrib><creatorcontrib>Kuo-Pin Chang</creatorcontrib><creatorcontrib>Yi-Hsuan Hsiao</creatorcontrib><creatorcontrib>Tzu-Hsuan Hsu</creatorcontrib><creatorcontrib>Chih-Ping Chen</creatorcontrib><creatorcontrib>Yin-Jen Chen</creatorcontrib><creatorcontrib>Kuan-Fu Chen</creatorcontrib><creatorcontrib>Lo, Chester</creatorcontrib><creatorcontrib>Tzung-Ting Han</creatorcontrib><creatorcontrib>Ming-Shiang Chen</creatorcontrib><creatorcontrib>Wen-Pin Lu</creatorcontrib><creatorcontrib>Szu-Yu Wang</creatorcontrib><creatorcontrib>Jeng-Hwa Liao</creatorcontrib><creatorcontrib>Shih-Ping Hong</creatorcontrib><creatorcontrib>Fang-Hao Hsu</creatorcontrib><creatorcontrib>Tahone Yang</creatorcontrib><creatorcontrib>Kuang-Chao Chen</creatorcontrib><creatorcontrib>Kuang-Yeu Hsieh</creatorcontrib><creatorcontrib>Chih-Yuan Lu</creatorcontrib><title>A novel BE-SONOS NAND Flash using non-cut trapping layer with superb reliability</title><title>2010 International Electron Devices Meeting</title><addtitle>IEDM</addtitle><description>This work presents superb chip-level reliability of a BE-SONOS charge trapping NAND fabricated in both 75nm and 38nm half-pitches. Without any error correction (ECC) >;100K P/E cycling endurance for SLC and >;3K endurance for MLC are obtained using a novel non-cut SiN trapping layer. Key process integration strategies are discussed, including barrier and trapping layer engineering, p-well and junction doping optimization, gate-etching profile, and SSL/GSL processing. In addition to the overall good performance in programming/erasing and reliability, the non-cut SiN also demonstrated charge retention without any lateral spread - contrary to common misperception of charge migration in SiN. We believe this is the first time the reliability and performance of a charge trapping NAND chip are demonstrated to match or surpass those for FG NAND.</description><subject>Charge carrier processes</subject><subject>Degradation</subject><subject>Doping</subject><subject>Logic gates</subject><subject>Reliability</subject><subject>Silicon compounds</subject><subject>Stress</subject><issn>0163-1918</issn><issn>2156-017X</issn><isbn>9781442474185</isbn><isbn>1442474181</isbn><isbn>9781424474196</isbn><isbn>1424474191</isbn><isbn>1424474205</isbn><isbn>9781424474202</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkElOwzAYhc1QiVB6AMTGF3DxbzselqEDVCoNUrtgVzmOQ41CiZK0qLfHiK7e8Elv8RC6BzoGoOZxMZu-jhmNMVWUc8ov0MgoDYIJoQQYeYkSBqkkFNT71ZlFGJlOr1FCQXICBvQAJRqIFIxpcYNuu-6TUqZSkyboLcP776Ov8dOMrPNVvsarbDXF89p2O3zowv4j8j1xhx73rW2av6K2J9_in9DvcHdofFvg1tfBFqEO_ekODSpbd3501iHazGebyQtZ5s-LSbYkwdCeaOoUlEpqbQvuRQVGFUJ6BpY7ykvHS-srXklXghHRl455yXSs4xXGCT5ED_-zwXu_bdrwZdvT9vwT_wX481Tz</recordid><startdate>201012</startdate><enddate>201012</enddate><creator>Chih-Chang Hsieh</creator><creator>Hang-Ting Lue</creator><creator>Kuo-Pin Chang</creator><creator>Yi-Hsuan Hsiao</creator><creator>Tzu-Hsuan Hsu</creator><creator>Chih-Ping Chen</creator><creator>Yin-Jen Chen</creator><creator>Kuan-Fu Chen</creator><creator>Lo, Chester</creator><creator>Tzung-Ting Han</creator><creator>Ming-Shiang Chen</creator><creator>Wen-Pin Lu</creator><creator>Szu-Yu Wang</creator><creator>Jeng-Hwa Liao</creator><creator>Shih-Ping Hong</creator><creator>Fang-Hao Hsu</creator><creator>Tahone Yang</creator><creator>Kuang-Chao Chen</creator><creator>Kuang-Yeu Hsieh</creator><creator>Chih-Yuan Lu</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>201012</creationdate><title>A novel BE-SONOS NAND Flash using non-cut trapping layer with superb reliability</title><author>Chih-Chang Hsieh ; Hang-Ting Lue ; Kuo-Pin Chang ; Yi-Hsuan Hsiao ; Tzu-Hsuan Hsu ; Chih-Ping Chen ; Yin-Jen Chen ; Kuan-Fu Chen ; Lo, Chester ; Tzung-Ting Han ; Ming-Shiang Chen ; Wen-Pin Lu ; Szu-Yu Wang ; Jeng-Hwa Liao ; Shih-Ping Hong ; Fang-Hao Hsu ; Tahone Yang ; Kuang-Chao Chen ; Kuang-Yeu Hsieh ; Chih-Yuan Lu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-80c71d7688ab3e4f197b46e21a3c03dc3daef3f6cd194daedc2e6283da5709c43</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Charge carrier processes</topic><topic>Degradation</topic><topic>Doping</topic><topic>Logic gates</topic><topic>Reliability</topic><topic>Silicon compounds</topic><topic>Stress</topic><toplevel>online_resources</toplevel><creatorcontrib>Chih-Chang Hsieh</creatorcontrib><creatorcontrib>Hang-Ting Lue</creatorcontrib><creatorcontrib>Kuo-Pin Chang</creatorcontrib><creatorcontrib>Yi-Hsuan Hsiao</creatorcontrib><creatorcontrib>Tzu-Hsuan Hsu</creatorcontrib><creatorcontrib>Chih-Ping Chen</creatorcontrib><creatorcontrib>Yin-Jen Chen</creatorcontrib><creatorcontrib>Kuan-Fu Chen</creatorcontrib><creatorcontrib>Lo, Chester</creatorcontrib><creatorcontrib>Tzung-Ting Han</creatorcontrib><creatorcontrib>Ming-Shiang Chen</creatorcontrib><creatorcontrib>Wen-Pin Lu</creatorcontrib><creatorcontrib>Szu-Yu Wang</creatorcontrib><creatorcontrib>Jeng-Hwa Liao</creatorcontrib><creatorcontrib>Shih-Ping Hong</creatorcontrib><creatorcontrib>Fang-Hao Hsu</creatorcontrib><creatorcontrib>Tahone Yang</creatorcontrib><creatorcontrib>Kuang-Chao Chen</creatorcontrib><creatorcontrib>Kuang-Yeu Hsieh</creatorcontrib><creatorcontrib>Chih-Yuan Lu</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Explore</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chih-Chang Hsieh</au><au>Hang-Ting Lue</au><au>Kuo-Pin Chang</au><au>Yi-Hsuan Hsiao</au><au>Tzu-Hsuan Hsu</au><au>Chih-Ping Chen</au><au>Yin-Jen Chen</au><au>Kuan-Fu Chen</au><au>Lo, Chester</au><au>Tzung-Ting Han</au><au>Ming-Shiang Chen</au><au>Wen-Pin Lu</au><au>Szu-Yu Wang</au><au>Jeng-Hwa Liao</au><au>Shih-Ping Hong</au><au>Fang-Hao Hsu</au><au>Tahone Yang</au><au>Kuang-Chao Chen</au><au>Kuang-Yeu Hsieh</au><au>Chih-Yuan Lu</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A novel BE-SONOS NAND Flash using non-cut trapping layer with superb reliability</atitle><btitle>2010 International Electron Devices Meeting</btitle><stitle>IEDM</stitle><date>2010-12</date><risdate>2010</risdate><spage>5.5.1</spage><epage>5.5.4</epage><pages>5.5.1-5.5.4</pages><issn>0163-1918</issn><eissn>2156-017X</eissn><isbn>9781442474185</isbn><isbn>1442474181</isbn><eisbn>9781424474196</eisbn><eisbn>1424474191</eisbn><eisbn>1424474205</eisbn><eisbn>9781424474202</eisbn><abstract>This work presents superb chip-level reliability of a BE-SONOS charge trapping NAND fabricated in both 75nm and 38nm half-pitches. Without any error correction (ECC) >;100K P/E cycling endurance for SLC and >;3K endurance for MLC are obtained using a novel non-cut SiN trapping layer. Key process integration strategies are discussed, including barrier and trapping layer engineering, p-well and junction doping optimization, gate-etching profile, and SSL/GSL processing. In addition to the overall good performance in programming/erasing and reliability, the non-cut SiN also demonstrated charge retention without any lateral spread - contrary to common misperception of charge migration in SiN. We believe this is the first time the reliability and performance of a charge trapping NAND chip are demonstrated to match or surpass those for FG NAND.</abstract><pub>IEEE</pub><doi>10.1109/IEDM.2010.5703303</doi></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0163-1918 |
| ispartof | 2010 International Electron Devices Meeting, 2010, p.5.5.1-5.5.4 |
| issn | 0163-1918 2156-017X |
| language | eng |
| recordid | cdi_ieee_primary_5703303 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Charge carrier processes Degradation Doping Logic gates Reliability Silicon compounds Stress |
| title | A novel BE-SONOS NAND Flash using non-cut trapping layer with superb reliability |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-14T17%3A46%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%20novel%20BE-SONOS%20NAND%20Flash%20using%20non-cut%20trapping%20layer%20with%20superb%20reliability&rft.btitle=2010%20International%20Electron%20Devices%20Meeting&rft.au=Chih-Chang%20Hsieh&rft.date=2010-12&rft.spage=5.5.1&rft.epage=5.5.4&rft.pages=5.5.1-5.5.4&rft.issn=0163-1918&rft.eissn=2156-017X&rft.isbn=9781442474185&rft.isbn_list=1442474181&rft_id=info:doi/10.1109/IEDM.2010.5703303&rft_dat=%3Cieee_6IE%3E5703303%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424474196&rft.eisbn_list=1424474191&rft.eisbn_list=1424474205&rft.eisbn_list=9781424474202&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=5703303&rfr_iscdi=true |