Product drift from NBTI: Guardbanding, circuit and statistical effects

Circuits employing advanced performance and power management techniques (clock gating, half-cycle paths) are found to be much more sensitive to NBTI primarily due to differential and asymmetric aging, with a 1% transistor drift leading to as much as 3% circuit drift in some cases. For the first time...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Krishnan, A T, Cano, F, Chancellor, C, Reddy, V, Zhangfen Qi, Jain, P, Carulli, J, Masin, J, Zuhoski, S, Krishnan, S, Ondrusek, J
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Clocks Degradation Delay Integrated circuit modeling IP networks Stress Transistors
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