Product drift from NBTI: Guardbanding, circuit and statistical effects
Circuits employing advanced performance and power management techniques (clock gating, half-cycle paths) are found to be much more sensitive to NBTI primarily due to differential and asymmetric aging, with a 1% transistor drift leading to as much as 3% circuit drift in some cases. For the first time...
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| creator | Krishnan, A T Cano, F Chancellor, C Reddy, V Zhangfen Qi Jain, P Carulli, J Masin, J Zuhoski, S Krishnan, S Ondrusek, J |
| description | Circuits employing advanced performance and power management techniques (clock gating, half-cycle paths) are found to be much more sensitive to NBTI primarily due to differential and asymmetric aging, with a 1% transistor drift leading to as much as 3% circuit drift in some cases. For the first time, we report a monotonic reduction in variance of the log parameters (Ln(ΔF/F) and Ln(ΔI D /I D )) as a function of stress time. A stochastic guard banding model accounting for time-dependent variance, re-ordering effects and granularity of data is demonstrated. |
| doi_str_mv | 10.1109/IEDM.2010.5703294 |
| format | Conference Proceeding |
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| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0163-1918 |
| ispartof | 2010 International Electron Devices Meeting, 2010, p.4.3.1-4.3.4 |
| issn | 0163-1918 2156-017X |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Clocks Degradation Delay Integrated circuit modeling IP networks Stress Transistors |
| title | Product drift from NBTI: Guardbanding, circuit and statistical effects |
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