Work-function engineering in gate first technology for multi-VT dual-gate FDSOI CMOS on UTBOX
For the first time, we demonstrate low-V T (V Tlin ±0.32V) nMOS and pMOS adjusted in a gate first FDSOI technology by work-function engineering of TiN/TaAlN metal gates. Especially, for low-V T pMOS, various Chemical-Vapor-Deposited TaAlN stacks with optimized Al concentration have been studied to f...
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| creator | Weber, O Andrieu, F Mazurier, J Cassé, M Garros, X Leroux, C Martin, F Perreau, P Fenouillet-Béranger, C Barnola, S Gassilloud, R Arvet, C Thomas, O Noel, J.-P Rozeau, O Jaud, M.-A Poiroux, T Lafond, D Toffoli, A Allain, F Tabone, C Tosti, L Brévard, L Lehnen, P Weber, U Baumann, P K Boissiere, O Schwarzenbach, W Bourdelle, K Nguyen, B.-Y Boeuf, F Skotnicki, T Faynot, O |
| description | For the first time, we demonstrate low-V T (V Tlin ±0.32V) nMOS and pMOS adjusted in a gate first FDSOI technology by work-function engineering of TiN/TaAlN metal gates. Especially, for low-V T pMOS, various Chemical-Vapor-Deposited TaAlN stacks with optimized Al concentration have been studied to finely tune the work-function above midgap while maintaining good reliability and mobility. Short channel performance of 500μA/μm I ON and 245μA/μm I EFF at 2nA/μm I OFF and V DD =0.9 V is reported on pMOS with a TaAlN gate. In addition, it is found that the combination of these two metal gates with either n- or p-doped ground planes below the Ultra-Thin Buried Oxide (BOX) can offer 4 different V T from 0.32 V to 0.6 V for both nMOS and pMOS, demonstrating a real multiple-V T capability for FDSOI CMOS while keeping the channel undoped and the V T variability around A VT =1.3mV.μm. |
| doi_str_mv | 10.1109/IEDM.2010.5703289 |
| format | Conference Proceeding |
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| subjects | Logic gates MOS devices MOSFET circuits Random access memory Silicon Tin |
| title | Work-function engineering in gate first technology for multi-VT dual-gate FDSOI CMOS on UTBOX |
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