CUSPARC IP processor: Design, characterization and applications
In this paper, we introduce the design of an IP processor core code-named CUSPARC for Cairo university SPARC processor. This core is a 32 bit pipelined processor that conforms to SPARC v8 ISA. It is complete with 4 register windows, I and D caches, SRAM and flash memory controller, resolution hardwa...
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| creator | Hussein, Ezz El-Din O. Shams, Shoukry I. Ali, Mohamed I. Suleiman, Amr A. Z. ElWazeer, Khalid Sobhy, Ehab A. Ibrahim, Ahmad A. I. Ibrahim, Ahmed M. G. Khairy, Mohamed S. Fouda, Mohamed F. El-Shafie, Al-Hussein A. Hareedy, Ahmed H. M. Ahmed, ElSayed A. Zakaria, Ahmed R. El-Galaind, Khalid M. Sherief, Amr A. El Habib, S. E.-D. |
| description | In this paper, we introduce the design of an IP processor core code-named CUSPARC for Cairo university SPARC processor. This core is a 32 bit pipelined processor that conforms to SPARC v8 ISA. It is complete with 4 register windows, I and D caches, SRAM and flash memory controller, resolution hardware for the data and branch hazards, interrupts and exception handling, instructions to support I/O transfers, and two standard WISHBONE buses to support high speed and low speed IO transfers. The design was downloaded and tested on different FPGA platforms, in addition to 0.35μm and 0.13μm ASIC technologies. CUSPARC has a promising metric of 0.9663 DMIPS/MHz. A novel debugger tool was developed for validating CUSPARC. This tool facilitates the testing of the processor running complex software loads by invoking Mentor's MODELSIM simulator in the background while maintaining a "simulator-like" GUI in the foreground. |
| doi_str_mv | 10.1109/ICM.2010.5696181 |
| format | Conference Proceeding |
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This tool facilitates the testing of the processor running complex software loads by invoking Mentor's MODELSIM simulator in the background while maintaining a "simulator-like" GUI in the foreground.</description><subject>Computer architecture</subject><subject>CUSPARC</subject><subject>Field programmable gate arrays</subject><subject>IP processor</subject><subject>Measurement</subject><subject>processor design</subject><subject>Random access memory</subject><subject>Real time systems</subject><subject>Registers</subject><subject>Software</subject><subject>SPARC</subject><issn>2159-1660</issn><isbn>9781612841496</isbn><isbn>161284149X</isbn><isbn>9781612841519</isbn><isbn>9781612841502</isbn><isbn>1612841503</isbn><isbn>1612841511</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpN0L1OwzAUBWAjQKIq2ZFY8gCk-Nq5dsyCqvAXqYgK6Fw59i0YlSSys8DTU0EHznL0LWc4jJ0BnwFwc9nUjzPBd0JlFFRwwDKjK1AgqhIQzOF_l0YdsYkANAUoxU9YltIH3wWFrlBP2HW9elnOn-u8WeZD7B2l1Mer_IZSeOsucvduo3UjxfBtx9B3ue18bodhG9yv0yk73thtomzfU7a6u32tH4rF031TzxdFAI1jIaxpRVtqRAXao1JOemwF10DStJ681qYlCdxuHHhPSCikdsYatKQtySk7_9sNRLQeYvi08Wu9v0D-AE1RTAo</recordid><startdate>201012</startdate><enddate>201012</enddate><creator>Hussein, Ezz El-Din O.</creator><creator>Shams, Shoukry I.</creator><creator>Ali, Mohamed I.</creator><creator>Suleiman, Amr A. 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M. ; Ahmed, ElSayed A. ; Zakaria, Ahmed R. ; El-Galaind, Khalid M. ; Sherief, Amr A. El ; Habib, S. E.-D.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-2a9b2b4755617d566c3d5b2071e39bded779be310afc1dde5e5237c9a95ae7ae3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>Computer architecture</topic><topic>CUSPARC</topic><topic>Field programmable gate arrays</topic><topic>IP processor</topic><topic>Measurement</topic><topic>processor design</topic><topic>Random access memory</topic><topic>Real time systems</topic><topic>Registers</topic><topic>Software</topic><topic>SPARC</topic><toplevel>online_resources</toplevel><creatorcontrib>Hussein, Ezz El-Din O.</creatorcontrib><creatorcontrib>Shams, Shoukry I.</creatorcontrib><creatorcontrib>Ali, Mohamed I.</creatorcontrib><creatorcontrib>Suleiman, Amr A. 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E.-D.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hussein, Ezz El-Din O.</au><au>Shams, Shoukry I.</au><au>Ali, Mohamed I.</au><au>Suleiman, Amr A. Z.</au><au>ElWazeer, Khalid</au><au>Sobhy, Ehab A.</au><au>Ibrahim, Ahmad A. I.</au><au>Ibrahim, Ahmed M. G.</au><au>Khairy, Mohamed S.</au><au>Fouda, Mohamed F.</au><au>El-Shafie, Al-Hussein A.</au><au>Hareedy, Ahmed H. M.</au><au>Ahmed, ElSayed A.</au><au>Zakaria, Ahmed R.</au><au>El-Galaind, Khalid M.</au><au>Sherief, Amr A. El</au><au>Habib, S. E.-D.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>CUSPARC IP processor: Design, characterization and applications</atitle><btitle>2010 International Conference on Microelectronics</btitle><stitle>ICM</stitle><date>2010-12</date><risdate>2010</risdate><spage>435</spage><epage>438</epage><pages>435-438</pages><issn>2159-1660</issn><isbn>9781612841496</isbn><isbn>161284149X</isbn><eisbn>9781612841519</eisbn><eisbn>9781612841502</eisbn><eisbn>1612841503</eisbn><eisbn>1612841511</eisbn><abstract>In this paper, we introduce the design of an IP processor core code-named CUSPARC for Cairo university SPARC processor. This core is a 32 bit pipelined processor that conforms to SPARC v8 ISA. It is complete with 4 register windows, I and D caches, SRAM and flash memory controller, resolution hardware for the data and branch hazards, interrupts and exception handling, instructions to support I/O transfers, and two standard WISHBONE buses to support high speed and low speed IO transfers. The design was downloaded and tested on different FPGA platforms, in addition to 0.35μm and 0.13μm ASIC technologies. CUSPARC has a promising metric of 0.9663 DMIPS/MHz. A novel debugger tool was developed for validating CUSPARC. This tool facilitates the testing of the processor running complex software loads by invoking Mentor's MODELSIM simulator in the background while maintaining a "simulator-like" GUI in the foreground.</abstract><pub>IEEE</pub><doi>10.1109/ICM.2010.5696181</doi><tpages>4</tpages></addata></record> |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Computer architecture CUSPARC Field programmable gate arrays IP processor Measurement processor design Random access memory Real time systems Registers Software SPARC |
| title | CUSPARC IP processor: Design, characterization and applications |
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