Adaptive Low Shift Power Test Pattern Generator for Logic BIST
Increasing the correlation among adjacent test stimulus bits can significantly reduce shift power consumption. However, it often causes test coverage loss when applying it to reduce the shift power consumption in logic BIST. In this paper, a new adaptive low shift power random test pattern generator...
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| creator | Xijiang Lin Rajski, J |
| description | Increasing the correlation among adjacent test stimulus bits can significantly reduce shift power consumption. However, it often causes test coverage loss when applying it to reduce the shift power consumption in logic BIST. In this paper, a new adaptive low shift power random test pattern generator (ALP-RTPG) is presented to improve the tradeoff between test coverage loss and shift power reduction in logic BIST. This is achieved by applying the information derived from test responses to dynamically adjust the correlation among adjacent test stimulus bits. When comparing with an existing method, called LT-RTPG, experimental results for industrial designs show that the proposed method can significantly reduce the test coverage loss while still achieving dramatic shift power reduction. |
| doi_str_mv | 10.1109/ATS.2010.67 |
| format | Conference Proceeding |
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However, it often causes test coverage loss when applying it to reduce the shift power consumption in logic BIST. In this paper, a new adaptive low shift power random test pattern generator (ALP-RTPG) is presented to improve the tradeoff between test coverage loss and shift power reduction in logic BIST. This is achieved by applying the information derived from test responses to dynamically adjust the correlation among adjacent test stimulus bits. When comparing with an existing method, called LT-RTPG, experimental results for industrial designs show that the proposed method can significantly reduce the test coverage loss while still achieving dramatic shift power reduction.</description><identifier>ISSN: 1081-7735</identifier><identifier>ISBN: 1424488419</identifier><identifier>ISBN: 9781424488414</identifier><identifier>EISSN: 2377-5386</identifier><identifier>DOI: 10.1109/ATS.2010.67</identifier><language>eng</language><publisher>IEEE</publisher><subject>BIST ; Built-in self-test ; Computer architecture ; Logic gates ; low power ; Microprocessors ; Power control ; Power demand ; scan shift ; scan test ; Switches</subject><ispartof>2010 19th IEEE Asian Test Symposium, 2010, p.355-360</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5692272$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5692272$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Xijiang Lin</creatorcontrib><creatorcontrib>Rajski, J</creatorcontrib><title>Adaptive Low Shift Power Test Pattern Generator for Logic BIST</title><title>2010 19th IEEE Asian Test Symposium</title><addtitle>ats</addtitle><description>Increasing the correlation among adjacent test stimulus bits can significantly reduce shift power consumption. However, it often causes test coverage loss when applying it to reduce the shift power consumption in logic BIST. In this paper, a new adaptive low shift power random test pattern generator (ALP-RTPG) is presented to improve the tradeoff between test coverage loss and shift power reduction in logic BIST. This is achieved by applying the information derived from test responses to dynamically adjust the correlation among adjacent test stimulus bits. When comparing with an existing method, called LT-RTPG, experimental results for industrial designs show that the proposed method can significantly reduce the test coverage loss while still achieving dramatic shift power reduction.</description><subject>BIST</subject><subject>Built-in self-test</subject><subject>Computer architecture</subject><subject>Logic gates</subject><subject>low power</subject><subject>Microprocessors</subject><subject>Power control</subject><subject>Power demand</subject><subject>scan shift</subject><subject>scan test</subject><subject>Switches</subject><issn>1081-7735</issn><issn>2377-5386</issn><isbn>1424488419</isbn><isbn>9781424488414</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjk1LAzEYhIMf4Fp78uglf2Brvt_kIqxFa2FBYddzSdM3GtFuyQaL_94FHRjmmcswhFxztuCcudum7xaCTc3ACamEBKi1tOaUXHIllLJWcXdGKs4srwGkviDzcfxgk7QABVCRu2bnDyV9I22HI-3eUyz0ZThipj2OE_pSMO_pCveYfRkyjZPb4S0Fer_u-ityHv3niPP_nJHXx4d--VS3z6v1smnrJBQvtQkq2oAenDfeoHHKW7AQIjJlAzcatmAjyun0zvmwFVwqkFYoZr1gWssZufnbTYi4OeT05fPPRhsnBAj5CxP8R5w</recordid><startdate>201012</startdate><enddate>201012</enddate><creator>Xijiang Lin</creator><creator>Rajski, J</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201012</creationdate><title>Adaptive Low Shift Power Test Pattern Generator for Logic BIST</title><author>Xijiang Lin ; Rajski, J</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i241t-6c4f8cea79a6a6e694a8787cfe048c1657b78fe3424d9acb21347382408a20553</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>BIST</topic><topic>Built-in self-test</topic><topic>Computer architecture</topic><topic>Logic gates</topic><topic>low power</topic><topic>Microprocessors</topic><topic>Power control</topic><topic>Power demand</topic><topic>scan shift</topic><topic>scan test</topic><topic>Switches</topic><toplevel>online_resources</toplevel><creatorcontrib>Xijiang Lin</creatorcontrib><creatorcontrib>Rajski, J</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Xijiang Lin</au><au>Rajski, J</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Adaptive Low Shift Power Test Pattern Generator for Logic BIST</atitle><btitle>2010 19th IEEE Asian Test Symposium</btitle><stitle>ats</stitle><date>2010-12</date><risdate>2010</risdate><spage>355</spage><epage>360</epage><pages>355-360</pages><issn>1081-7735</issn><eissn>2377-5386</eissn><isbn>1424488419</isbn><isbn>9781424488414</isbn><abstract>Increasing the correlation among adjacent test stimulus bits can significantly reduce shift power consumption. However, it often causes test coverage loss when applying it to reduce the shift power consumption in logic BIST. In this paper, a new adaptive low shift power random test pattern generator (ALP-RTPG) is presented to improve the tradeoff between test coverage loss and shift power reduction in logic BIST. This is achieved by applying the information derived from test responses to dynamically adjust the correlation among adjacent test stimulus bits. When comparing with an existing method, called LT-RTPG, experimental results for industrial designs show that the proposed method can significantly reduce the test coverage loss while still achieving dramatic shift power reduction.</abstract><pub>IEEE</pub><doi>10.1109/ATS.2010.67</doi><tpages>6</tpages></addata></record> |
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| issn | 1081-7735 2377-5386 |
| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | BIST Built-in self-test Computer architecture Logic gates low power Microprocessors Power control Power demand scan shift scan test Switches |
| title | Adaptive Low Shift Power Test Pattern Generator for Logic BIST |
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