Design of a 256-KBit EEPROM IP for touch-screen controllers
We propose a compact design having low-power and high-speed EEPROM for touch-screen controller ICs. To optimize a small-area EEPROM design, a SSTC (side-wall selective transistor) cell is proposed which involves repeated high-voltage switching circuits inside the EEPROM core circuit. A digital data-...
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| creator | Gyu-Sam Cho Du-Hwi Kim Ji-Hye Jang Moo-Hun Park Pan-Bong Ha Young-Hee Kim Jung-Hwan Lee |
| description | We propose a compact design having low-power and high-speed EEPROM for touch-screen controller ICs. To optimize a small-area EEPROM design, a SSTC (side-wall selective transistor) cell is proposed which involves repeated high-voltage switching circuits inside the EEPROM core circuit. A digital data-bus sensing amplifier circuit is proposed as a low-power technology. For high speed, the distributed data-bus scheme is applied, and the driving voltage for both the EEPROM cell and the high-voltage switching circuits uses VDDP (=3.3V) which is higher than the logic voltage, VDD (=1.8V), using a dual power supply. 256-KBit EEPROM IP is designed using MagnaChip's 0.18μm EEPROM process. The layout size of the designed 256-KBit EEPROM IP is 1765.05 μm × 691.71 μm. |
| doi_str_mv | 10.1109/ICCE.2010.5670695 |
| format | Conference Proceeding |
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To optimize a small-area EEPROM design, a SSTC (side-wall selective transistor) cell is proposed which involves repeated high-voltage switching circuits inside the EEPROM core circuit. A digital data-bus sensing amplifier circuit is proposed as a low-power technology. For high speed, the distributed data-bus scheme is applied, and the driving voltage for both the EEPROM cell and the high-voltage switching circuits uses VDDP (=3.3V) which is higher than the logic voltage, VDD (=1.8V), using a dual power supply. 256-KBit EEPROM IP is designed using MagnaChip's 0.18μm EEPROM process. The layout size of the designed 256-KBit EEPROM IP is 1765.05 μm × 691.71 μm.</description><identifier>ISBN: 9781424470556</identifier><identifier>ISBN: 1424470552</identifier><identifier>EISBN: 1424470587</identifier><identifier>EISBN: 1424470579</identifier><identifier>EISBN: 9781424470570</identifier><identifier>EISBN: 9781424470587</identifier><identifier>DOI: 10.1109/ICCE.2010.5670695</identifier><language>eng</language><publisher>IEEE</publisher><subject>asynchronous interface ; digital sensing ; distributed data bus ; EEPROM ; EPROM ; high-speed ; IP networks ; Layout ; low-power ; Sensors ; small-area ; Switches ; Switching circuits ; Touch-Screen Controller ; Transistors</subject><ispartof>International Conference on Communications and Electronics 2010, 2010, p.124-126</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/5670695$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/5670695$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Gyu-Sam Cho</creatorcontrib><creatorcontrib>Du-Hwi Kim</creatorcontrib><creatorcontrib>Ji-Hye Jang</creatorcontrib><creatorcontrib>Moo-Hun Park</creatorcontrib><creatorcontrib>Pan-Bong Ha</creatorcontrib><creatorcontrib>Young-Hee Kim</creatorcontrib><creatorcontrib>Jung-Hwan Lee</creatorcontrib><title>Design of a 256-KBit EEPROM IP for touch-screen controllers</title><title>International Conference on Communications and Electronics 2010</title><addtitle>ICCE</addtitle><description>We propose a compact design having low-power and high-speed EEPROM for touch-screen controller ICs. To optimize a small-area EEPROM design, a SSTC (side-wall selective transistor) cell is proposed which involves repeated high-voltage switching circuits inside the EEPROM core circuit. A digital data-bus sensing amplifier circuit is proposed as a low-power technology. For high speed, the distributed data-bus scheme is applied, and the driving voltage for both the EEPROM cell and the high-voltage switching circuits uses VDDP (=3.3V) which is higher than the logic voltage, VDD (=1.8V), using a dual power supply. 256-KBit EEPROM IP is designed using MagnaChip's 0.18μm EEPROM process. The layout size of the designed 256-KBit EEPROM IP is 1765.05 μm × 691.71 μm.</description><subject>asynchronous interface</subject><subject>digital sensing</subject><subject>distributed data bus</subject><subject>EEPROM</subject><subject>EPROM</subject><subject>high-speed</subject><subject>IP networks</subject><subject>Layout</subject><subject>low-power</subject><subject>Sensors</subject><subject>small-area</subject><subject>Switches</subject><subject>Switching circuits</subject><subject>Touch-Screen Controller</subject><subject>Transistors</subject><isbn>9781424470556</isbn><isbn>1424470552</isbn><isbn>1424470587</isbn><isbn>1424470579</isbn><isbn>9781424470570</isbn><isbn>9781424470587</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2010</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNo1j81KxDAURiMiqGMfQNzkBTrem__gSmvV4sgMoushTROt1FaSuvDtHXA8m4-z-eAQco6wRAR72VRVvWSwU6k0KCsPyCkKJoQGafQhKaw2_y7VMSly_oAdkmkuxAm5ug25fxvpFKmjTKry8aafaV1vntdPtNnQOCU6T9_-vcw-hTBSP41zmoYhpHxGjqIbcij2uyCvd_VL9VCu1vdNdb0qe9RyLk2MrbDWMy84AhrhOoYBBXotpHYdOt4iaOakkmBYNFZFzzvWBrAQbeQLcvH324cQtl-p_3TpZ7vv5b8-OEXB</recordid><startdate>201008</startdate><enddate>201008</enddate><creator>Gyu-Sam Cho</creator><creator>Du-Hwi Kim</creator><creator>Ji-Hye Jang</creator><creator>Moo-Hun Park</creator><creator>Pan-Bong Ha</creator><creator>Young-Hee Kim</creator><creator>Jung-Hwan Lee</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>201008</creationdate><title>Design of a 256-KBit EEPROM IP for touch-screen controllers</title><author>Gyu-Sam Cho ; Du-Hwi Kim ; Ji-Hye Jang ; Moo-Hun Park ; Pan-Bong Ha ; Young-Hee Kim ; Jung-Hwan Lee</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-8ffb499c2c4310184ad21e141c7457ad1a3b1072a565082f896fc3d2be090f9f3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2010</creationdate><topic>asynchronous interface</topic><topic>digital sensing</topic><topic>distributed data bus</topic><topic>EEPROM</topic><topic>EPROM</topic><topic>high-speed</topic><topic>IP networks</topic><topic>Layout</topic><topic>low-power</topic><topic>Sensors</topic><topic>small-area</topic><topic>Switches</topic><topic>Switching circuits</topic><topic>Touch-Screen Controller</topic><topic>Transistors</topic><toplevel>online_resources</toplevel><creatorcontrib>Gyu-Sam Cho</creatorcontrib><creatorcontrib>Du-Hwi Kim</creatorcontrib><creatorcontrib>Ji-Hye Jang</creatorcontrib><creatorcontrib>Moo-Hun Park</creatorcontrib><creatorcontrib>Pan-Bong Ha</creatorcontrib><creatorcontrib>Young-Hee Kim</creatorcontrib><creatorcontrib>Jung-Hwan Lee</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Gyu-Sam Cho</au><au>Du-Hwi Kim</au><au>Ji-Hye Jang</au><au>Moo-Hun Park</au><au>Pan-Bong Ha</au><au>Young-Hee Kim</au><au>Jung-Hwan Lee</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Design of a 256-KBit EEPROM IP for touch-screen controllers</atitle><btitle>International Conference on Communications and Electronics 2010</btitle><stitle>ICCE</stitle><date>2010-08</date><risdate>2010</risdate><spage>124</spage><epage>126</epage><pages>124-126</pages><isbn>9781424470556</isbn><isbn>1424470552</isbn><eisbn>1424470587</eisbn><eisbn>1424470579</eisbn><eisbn>9781424470570</eisbn><eisbn>9781424470587</eisbn><abstract>We propose a compact design having low-power and high-speed EEPROM for touch-screen controller ICs. To optimize a small-area EEPROM design, a SSTC (side-wall selective transistor) cell is proposed which involves repeated high-voltage switching circuits inside the EEPROM core circuit. A digital data-bus sensing amplifier circuit is proposed as a low-power technology. For high speed, the distributed data-bus scheme is applied, and the driving voltage for both the EEPROM cell and the high-voltage switching circuits uses VDDP (=3.3V) which is higher than the logic voltage, VDD (=1.8V), using a dual power supply. 256-KBit EEPROM IP is designed using MagnaChip's 0.18μm EEPROM process. The layout size of the designed 256-KBit EEPROM IP is 1765.05 μm × 691.71 μm.</abstract><pub>IEEE</pub><doi>10.1109/ICCE.2010.5670695</doi><tpages>3</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISBN: 9781424470556 |
| ispartof | International Conference on Communications and Electronics 2010, 2010, p.124-126 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | asynchronous interface digital sensing distributed data bus EEPROM EPROM high-speed IP networks Layout low-power Sensors small-area Switches Switching circuits Touch-Screen Controller Transistors |
| title | Design of a 256-KBit EEPROM IP for touch-screen controllers |
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